DM74LS165N

DM74LS165N Datasheet

DM74LS165 8-Bit Parallel In/Serial Output Shift Registers

Part	Datasheet
DM74LS165N	DM74LS165N (pdf)

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DM74LS165 8-Bit Parallel In/Serial Output Shift Registers DM74LS165 8-Bit Parallel In/Serial Output Shift Registers This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. Parallel loading is inhibited as long as the load input is HIGH. Data at the parallel inputs are loaded directly into the register on a HIGH-to-LOW transition of the shift/load input, regardless of the logic levels on the clock, clock inhibit, or serial inputs. s Complementary outputs s Direct overriding data inputs s Gated clock inputs s Parallel-to-serial data conversion s Typical frequency 35 MHz s Typical power dissipation 105 mW Ordering Code: Order Number Package Number Package Description DM74LS165M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM74LS165WM M16B 16-Lead Small Outline Intergrated Circuit SOIC , JEDEC MS-013, Wide DM74LS165N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Internal Shift/ Clock Serial Parallel Outputs Output Load Inhibit A...H QA QB QH a...h a b X QA0 QB0 QH0 H QAn QGn L QAn QGn X QA0 QB0 QH0 H = HIGH Level steady state L = LOW Level steady state X = Don't Care any input, including transitions = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively. QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG, respectively, before the most recent transition of the clock. 2000 Fairchild Semiconductor Corporation DS006399 DM74LS165 Logic Diagram Timing Diagram Typical Shift, Load, and Inhibit Sequences DM74LS165 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 2 fCLK Clock Frequency Note 3 Pulse Width Clock

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DM74LS165 8-Bit Parallel In/Serial Output Shift Registers

DM74LS165 8-Bit Parallel In/Serial Output Shift Registers

This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit.

Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. Parallel loading is inhibited as long as the load input is HIGH. Data at the parallel inputs are loaded directly into the register on a HIGH-to-LOW transition of the shift/load input, regardless of the logic levels on the clock, clock inhibit, or serial inputs.
s Complementary outputs s Direct overriding data inputs s Gated clock inputs s Parallel-to-serial data conversion s Typical frequency 35 MHz s Typical power dissipation 105 mW
Ordering Code:

Order Number Package Number

Package Description

DM74LS165M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

DM74LS165WM

M16B
16-Lead Small Outline Intergrated Circuit SOIC , JEDEC MS-013, Wide

DM74LS165N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Internal

Shift/ Clock Serial Parallel Outputs Output

Load Inhibit

A...H QA QB QH
a...h a b

X QA0 QB0 QH0

H QAn QGn

L QAn QGn

X QA0 QB0 QH0

H = HIGH Level steady state L = LOW Level steady state X = Don't Care any input, including transitions = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively. QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the
indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG, respectively, before the most recent
transition of the clock.
2000 Fairchild Semiconductor Corporation DS006399

DM74LS165

Logic Diagram Timing Diagram

Typical Shift, Load, and Inhibit Sequences

DM74LS165

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 2
fCLK

Clock Frequency Note 3

Pulse Width

Clock

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Datasheet ID: DM74LS165N 513772