DM74AS286N

DM74AS286N Datasheet

DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port

Part	Datasheet
DM74AS286N	DM74AS286N (pdf)

Related Parts	Information
DM74AS286M	DM74AS286M
DM74AS286MX	DM74AS286MX

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DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port These universal, 9-bit parity generators/checkers utilize advanced Schottky high performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word length capability is easily expanded by cascading. The DM74AS286 can be used to upgrade the performance of most systems utilizing the DM74AS280 parity generator/ checker. Although the DM74AS286 is implemented without expander inputs, the corresponding function is provided by the availability of an input pin XMIT. XMIT is a control line which makes parity error output active and parity an input port when HIGH when LOW, parity error output is inactive and parity becomes an output port. In addition, parity I/O control circuitry contains a feature to keep the I/O port in the 3-STATE during power UP or DOWN to prevent bus glitches. s PNP inputs to reduce bus loading s Generates either odd or even parity for nine data lines s Inputs are buffered to lower the drive requirements s Can be used to upgrade existing systems using MSI parity circuits s Cascadable for n-bits s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s A parity I/O portable to drive bus Ordering Code: Order Number Package Number Package Description DM74AS286M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow DM74AS286N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Number of Inputs Parity I/O Parity Mode A thru I XMIT Error that are HIGH Input Output Operation 0, 2, 4, 6, 8 N/A H Parity 1, 3, 5, 7, 9 N/A L H Generator 0, 2, 4, 6, 8 H N/A H Parity 0, 2, 4, 6, 8 L N/A H L Checker 1, 3, 5, 7, 9 H N/A H Parity 1, 3, 5, 7, 9 L N/A H Checker L = LOW Logic Level H = HIGH Logic Level N/A = Not Applicable 2000 Fairchild Semiconductor Corporation DS006305 DM74AS286 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical N Package M Package 7V 0°C to +70°C −65°C to +150°C 77.0°C/W 108.0°C/W Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current

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DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port

DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port

These universal, 9-bit parity generators/checkers utilize advanced Schottky high performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word length capability is easily expanded by cascading.

The DM74AS286 can be used to upgrade the performance of most systems utilizing the DM74AS280 parity generator/ checker. Although the DM74AS286 is implemented without expander inputs, the corresponding function is provided by the availability of an input pin XMIT. XMIT is a control line which makes parity error output active and parity an input port when HIGH when LOW, parity error output is inactive and parity becomes an output port. In addition, parity I/O control circuitry contains a feature to keep the I/O port in the 3-STATE during power UP or DOWN to prevent bus glitches.
s PNP inputs to reduce bus loading s Generates either odd or even parity for nine data lines s Inputs are buffered to lower the drive requirements s Can be used to upgrade existing systems using MSI
parity circuits s Cascadable for n-bits s Switching specifications at 50 pF s Switching specifications guaranteed over full
temperature and VCC range s A parity I/O portable to drive bus
Ordering Code:

Order Number Package Number

Package Description

DM74AS286M

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow

DM74AS286N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Number of Inputs Parity I/O

Parity Mode

A thru I

XMIT Error
that are HIGH Input Output

Operation
0, 2, 4, 6, 8

N/A H

Parity
1, 3, 5, 7, 9

N/A L

H Generator
0, 2, 4, 6, 8

H N/A H

Parity
0, 2, 4, 6, 8

L N/A H

L Checker
1, 3, 5, 7, 9

H N/A H

Parity
1, 3, 5, 7, 9

L N/A H Checker

L = LOW Logic Level H = HIGH Logic Level N/A = Not Applicable
2000 Fairchild Semiconductor Corporation DS006305

DM74AS286

Absolute Maximum Ratings Note 1

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical

N Package M Package
7V 0°C to +70°C −65°C to +150°C
77.0°C/W 108.0°C/W

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

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Datasheet ID: DM74AS286N 513728