DM74ALS652WMX

DM74ALS652WMX Datasheet

DM74ALS652 Octal 3-STATE Bus Transceiver and Register

Part	Datasheet
DM74ALS652WMX	DM74ALS652WMX (pdf)

Related Parts	Information
DM74ALS652WM	DM74ALS652WM
DM74ALS652NT	DM74ALS652NT

PDF Datasheet Preview
DM74ALS652 Octal 3-STATE Bus Transceiver and Register DM74ALS652 Octal 3-STATE Bus Transceiver and Register This device incorporates an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus or internal register to bus. This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high level logic drive provide this device with the capability of being connected directly to and driving the bus lines in a bus organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The registers in the DM74ALS652 are edge-triggered D-type flip-flops. On the positive transition of the clock CAB or CBA , the input data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data. The enable GAB and GBA control pins provide four modes of operation real-time data transfer from bus A to B, real-time data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal stored data transfer to bus A and/or B. s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s 3-STATE buffer-type outputs drive bus lines directly s Independent registers and enables for A and B buses s Multiplexed real-time and stored data Ordering Code: Order Number Package Number Package Description DM74ALS652WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74ALS652NT N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram 2001 Fairchild Semiconductor Corporation DS009174 DM74ALS652 Function Table Inputs CAB CBA Data I/O Note 1 A1 thru A8 B1 thru B8 Operation or Function Input Not Specified Store A, Hold B X Not Specified Input Store B, Hold A Input Input Store A and B Data Input Input Isolation, Hold Storage Output Input Real-Time B Data to A Bus Output Input Stored B Data to A Bus Input Output Real-Time A Data to B Bus Input Output Stored A Data to B Bus Note 2 Input Output Store A in both Registers Output Note 2 Input Store B in both Registers H or L H or L Output Output Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Either LOW or HIGH Logic Levels, including transitions H/L = Either LOW or HIGH Logic Level excluding transitions = Positive-going edge of pulse

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DM74ALS652 Octal 3-STATE Bus Transceiver and Register

DM74ALS652 Octal 3-STATE Bus Transceiver and Register

This device incorporates an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus or internal register to bus.

This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high level logic drive provide this device with the capability of being connected directly to and driving the bus lines in a bus organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The registers in the DM74ALS652 are edge-triggered D-type flip-flops. On the positive transition of the clock CAB or CBA , the input data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register.

The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data.

The enable GAB and GBA control pins provide four modes of operation real-time data transfer from bus A to B, real-time data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal stored data transfer to bus A and/or B.
s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera-
ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL
process s 3-STATE buffer-type outputs drive bus lines directly s Independent registers and enables for A and B buses s Multiplexed real-time and stored data
Ordering Code:

Order Number Package Number

Package Description

DM74ALS652WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74ALS652NT

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
2001 Fairchild Semiconductor Corporation DS009174

DM74ALS652

Function Table

Inputs CAB CBA

Data I/O Note 1 A1 thru A8 B1 thru B8

Operation or Function

Input

Not Specified Store A, Hold B

X Not Specified

Input

Store B, Hold A

Input

Input

Store A and B Data

Input

Input

Isolation, Hold Storage

Output

Input

Real-Time B Data to A Bus

Output

Input

Stored B Data to A Bus

Input

Output Real-Time A Data to B Bus

Input

Output Stored A Data to B Bus

Note 2

Input

Output Store A in both Registers

Output

Note 2

Input

Store B in both Registers

H or L H or L

Output

Output

Stored A Data to B Bus and Stored B Data to A Bus

H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Either LOW or HIGH Logic Levels, including transitions H/L = Either LOW or HIGH Logic Level excluding transitions = Positive-going edge of pulse

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Datasheet ID: DM74ALS652WMX 513701