CD4538BCWMX

CD4538BCWMX Datasheet

CD4538BC Dual Precision Monostable

Part	Datasheet
CD4538BCWMX	CD4538BCWMX (pdf)

Related Parts	Information
CD4538BCWM	CD4538BCWM
CD4538BCN	CD4538BCN
CD4538BCM	CD4538BCM
CD4538BCMX	CD4538BCMX

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CD4538BC Dual Precision Monostable CD4538BC Dual Precision Monostable The CD4538BC is a dual, precision monostable multivibrator with independent trigger and reset controls. The device is retriggerable and resettable, and the control inputs are internally latched. Two trigger inputs are provided to allow either rising or falling edge triggering. The reset inputs are active LOW and prevent triggering while active. Precise control of output pulse-width has been achieved using linear CMOS techniques. The pulse duration and accuracy are determined by external components RX and CX. The device does not allow the timing capacitor to discharge through the timing pin on power-down condition. For this reason, no external protection resistor is required in series with the timing pin. Input protection from static discharge is provided on all pins. s Wide supply voltage range 3.0V to 15V s High noise immunity VCC typ. s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s New formula: PWOUT = RC PW in seconds, R in Ohms, C in Farads s pulse-width variation from part to part typ. s Wide pulse-width range 1 µs to ∞ s Separate latched reset inputs s Symmetrical output sink and source capability s Low standby current 5 nA typ. 5 VDC s Pin compatible to CD4528BC Ordering Code: Order Number Package Number Package Description CD4538BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4538BCWM M16B 16-Lead Small Outline Intergrated Circuit SOIC , JEDEC MS-013, Wide CD4538BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Top View Inputs Outputs Clear H = HIGH Level L = LOW Level = Transition from LOW-to-HIGH = Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant 2002 Fairchild Semiconductor Corporation DS006000 CD4538BC Block Diagram RX and CX are External Components VDD = Pin 16 VSS = Pin 8 Logic Diagram FIGURE CD4538BC Theory of Operation FIGURE Trigger Operation The block diagram of the CD4538BC is shown in Figure 1, with circuit operation following. As shown in Figure 1 and Figure 2, before an input trigger occurs, the monostable is in the quiescent state with the Q output low, and the timing capacitor CX completely charged to VDD. When the trigger input A goes from VSS to VDD while inputs B and CD are held to VDD a valid trigger is recognized, which turns on comparator C1 and N-Channel transistor N1 1 . At the same time the output latch is set. With transistor N1 on, the capacitor CX rapidly discharges toward VSS until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CX begins to charge through the timing resistor, RX, toward VDD. When the voltage across CX equals VREF2, comparator C2 changes state causing the output latch to reset Q goes low while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from VDD to VSS while input A is at VSS and input CD is at VDD 2 . Retrigger Operation The CD4538BC is retriggered if a valid trigger occurs 3 followed by another valid trigger 4 before the Q output has returned to the quiescent zero state. Any retrigger, after the timing node voltage at pin 2 or 14 has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated 4 , the voltage at T2 will again drop to VREF1 before progressing along the RC charging curve toward VDD. The Q output will remain high until time T, after the last valid retrigger. Reset Operation The CD4538BC may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on CD sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor Q1 5 . When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the CD input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the CD input, the output pulse T can be made significantly shorter than the minimum pulse width specification. CD4538BC FIGURE Retriggerable Monostables Circuitry FIGURE Non-Retriggerable Monostables Circuitry FIGURE Connection of Unused Sections CD4538BC Absolute Maximum Ratings Note 1 Note 2 DC Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL Soldering, 10 seconds to +18 VDC −0.5V to VDD + VDC −65°C to +150°C 700 mW 500 mW 260°C

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CD4538BC Dual Precision Monostable

CD4538BC Dual Precision Monostable

The CD4538BC is a dual, precision monostable multivibrator with independent trigger and reset controls. The device is retriggerable and resettable, and the control inputs are internally latched. Two trigger inputs are provided to allow either rising or falling edge triggering. The reset inputs are active LOW and prevent triggering while active. Precise control of output pulse-width has been achieved using linear CMOS techniques. The pulse duration and accuracy are determined by external components RX and CX. The device does not allow the timing capacitor to discharge through the timing pin on power-down condition. For this reason, no external protection resistor is required in series with the timing pin. Input protection from static discharge is provided on all pins.
s Wide supply voltage range 3.0V to 15V s High noise immunity VCC typ. s Low power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LS s New formula:

PWOUT = RC PW in seconds, R in Ohms, C in Farads s pulse-width variation from part to part typ. s Wide pulse-width range 1 µs to ∞ s Separate latched reset inputs s Symmetrical output sink and source capability s Low standby current 5 nA typ. 5 VDC s Pin compatible to CD4528BC
Ordering Code:

Order Number Package Number

Package Description

CD4538BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4538BCWM

M16B
16-Lead Small Outline Intergrated Circuit SOIC , JEDEC MS-013, Wide

CD4538BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Top View

Inputs

Outputs

Clear

H = HIGH Level L = LOW Level = Transition from LOW-to-HIGH
= Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant
2002 Fairchild Semiconductor Corporation DS006000

CD4538BC

Block Diagram

RX and CX are External Components VDD = Pin 16 VSS = Pin 8

Logic Diagram

FIGURE

CD4538BC

Theory of Operation

FIGURE

Trigger Operation

The block diagram of the CD4538BC is shown in Figure 1, with circuit operation following.

As shown in Figure 1 and Figure 2, before an input trigger occurs, the monostable is in the quiescent state with the Q output low, and the timing capacitor CX completely charged to VDD. When the trigger input A goes from VSS to VDD while inputs B and CD are held to VDD a valid trigger is recognized, which turns on comparator C1 and N-Channel transistor N1 1 . At the same time the output latch is set. With transistor N1 on, the capacitor CX rapidly discharges toward VSS until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CX begins to charge through the timing resistor, RX, toward VDD. When the voltage across CX equals VREF2, comparator C2 changes state causing the output latch to reset Q goes low while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger.

A valid trigger is also recognized when trigger input B goes from VDD to VSS while input A is at VSS and input CD is at VDD 2 .

Retrigger Operation

The CD4538BC is retriggered if a valid trigger occurs 3 followed by another valid trigger 4 before the Q output has returned to the quiescent zero state. Any retrigger, after the timing node voltage at pin 2 or 14 has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated 4 , the voltage at T2 will again drop to VREF1 before progressing along the RC charging curve toward VDD. The Q output will remain high until time T, after the last valid retrigger.

Reset Operation

The CD4538BC may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on CD sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor Q1 5 . When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the CD input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the CD input, the output pulse T can be made significantly shorter than the minimum pulse width specification.

CD4538BC

FIGURE Retriggerable Monostables Circuitry

FIGURE Non-Retriggerable Monostables Circuitry

FIGURE Connection of Unused Sections

CD4538BC

Absolute Maximum Ratings Note 1

Note 2

DC Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD

Dual-In-Line

Small Outline

Lead Temperature TL Soldering, 10 seconds
to +18 VDC −0.5V to VDD + VDC
−65°C to +150°C
700 mW 500 mW
260°C

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Datasheet ID: CD4538BCWMX 513586