CD4081BCN

CD4081BCN Datasheet

CD4071BC<br>• CD4081BC Quad 2-Input OR Buffered B Series Gate<br>• Quad 2-Input AND Buffered B Series Gate

Part	Datasheet
CD4081BCN	CD4081BCN (pdf)

Related Parts	Information
CD4071BCN	CD4071BCN

PDF Datasheet Preview
CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate The CD4071BC and CD4081BC quad gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs protected against static discharge with diodes to VDD and VSS. s Low power TTL compatibility Fan out of 2 driving 74L or 1 driving 74LS s parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full temperature range Ordering Code: Order Number Package Number Package Description CD4071BCM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4071BCN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide CD4081BCM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4081BCN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams CD4071B CD4081B Top View Top View 2002 Fairchild Semiconductor Corporation DS005977 CD4071BC • CD4081BC Schematic Diagrams CD4071B CD4081B 1/4 of device shown J=A+B Logical “1” = HIGH Logical “0” = LOW *All inputs protected by standard CMOS protection circuit. 1/4 of device shown J=A•B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. CD4071BC • CD4081BC Absolute Maximum Ratings Note 1 Note 2 Voltage at Any Pin Power Dissipation PD Dual-In-Line Small Outline VDD Range Storage Temperature TS Lead Temperature TL Soldering, 10 seconds −0.5V to VDD +0.5V 700 mW 500 mW VDC to +18 VDC −65°C to +150°C 260°C Recommended Operating Conditions Operating Range VDD Operating Temperature Range TA CD4071BC, CD4081BC 3 VDC to 15 VDC −55°C to +125°C Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2 All voltages measured with respect to VSS unless otherwise specified. DC Electrical Characteristics Note 2 CD4071BC/CD4081BC Parameter Conditions Quiescent Device VDD = 5V Current VDD = 10V VDD = 15V LOW Level VDD = 5V Output Voltage VDD = 10V \|IO\| < 1 µA VDD = 15V

PDF Datasheet Preview

CD4071BC
• CD4081BC Quad 2-Input OR Buffered B Series Gate
• Quad 2-Input AND Buffered B Series Gate

CD4071BC
• CD4081BC Quad 2-Input OR Buffered B Series Gate
• Quad 2-Input AND Buffered B Series Gate

The CD4071BC and CD4081BC quad gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain.

All inputs protected against static discharge with diodes to VDD and VSS.
s Low power TTL compatibility Fan out of 2 driving 74L or 1 driving 74LS
s parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full
temperature range
Ordering Code:

Order Number Package Number

Package Description

CD4071BCM

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4071BCN

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

CD4081BCM

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4081BCN

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

CD4071B

CD4081B

Top View

Top View
2002 Fairchild Semiconductor Corporation DS005977

CD4071BC
• CD4081BC

Schematic Diagrams CD4071B

CD4081B
1/4 of device shown J=A+B Logical “1” = HIGH Logical “0” = LOW *All inputs protected by standard CMOS protection circuit.
1/4 of device shown J=A•B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit.

CD4071BC
• CD4081BC

Absolute Maximum Ratings Note 1

Note 2

Voltage at Any Pin Power Dissipation PD

Dual-In-Line Small Outline VDD Range Storage Temperature TS Lead Temperature TL Soldering, 10 seconds
−0.5V to VDD +0.5V
700 mW 500 mW VDC to +18 VDC −65°C to +150°C
260°C

Recommended Operating Conditions

Operating Range VDD Operating Temperature Range TA

CD4071BC, CD4081BC
3 VDC to 15 VDC −55°C to +125°C

Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.

Note 2 All voltages measured with respect to VSS unless otherwise specified.

DC Electrical Characteristics Note 2

CD4071BC/CD4081BC

Parameter

Conditions

Quiescent Device

VDD = 5V

Current

VDD = 10V

VDD = 15V

LOW Level

VDD = 5V

Output Voltage

VDD = 10V
|IO| < 1 µA

VDD = 15V

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Datasheet ID: CD4081BCN 513577