CY62147EV18LL-45BVXI

CY62147EV18LL-45BVXI Datasheet


CY62147EV18 MoBL2

Part Datasheet
CY62147EV18LL-45BVXI CY62147EV18LL-45BVXI CY62147EV18LL-45BVXI (pdf)
Related Parts Information
CY62147EV18LL-45BVXIT CY62147EV18LL-45BVXIT CY62147EV18LL-45BVXIT
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CY62147EV18 MoBL2
• Very high speed 45 ns
• Wide voltage range
• Pin-compatible with CY62147DV18
• Ultra low standby power

Typical standby current 1 µA Maximum standby current 7 µA
• Ultra-low active power Typical active current 2 mA f = 1 MHz
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in a 48-ball Pb-free VFBGA package

Functional Description[1]

The CY62147EV18 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device

Logic Block Diagram
4-Mbit 256K x 16 Static RAM
also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected CE HIGH or both BLE and BHE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH , or during a write operation CE LOW and WE LOW .

Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A17 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A17 .

Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.

The CY62147EV18 is available in a 48-ball VFBGA package.

DATA IN DRIVERS

A10 A9

A8 A7
256K x 16

RAM Array

A2 A1 A0

ROW DECODER A11 A12 A13 A14 A15 A16 A17

SENSE AMPS

COLUMN DECODER

Power-down Circuit

CE BHE BLE

BHE WE

CE OE BLE

Note For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

Pin Configuration[2, 3]
48-ball VFBGA Pinout Top View

BLE OE A0 A1 A2 NC

I/O8 BHE A3 A4 CE I/O0

I/O9 I/O10 A5 A6 I/O1 I/O2

VSS I/O11 A17 A7 I/O3 Vcc

VCC I/O12 NC

A16 I/O4 Vss

I/O14 I/O13 A14 A15 I/O5 I/O6

I/O15 NC A12 A13 WE I/O7

NC A8 A9 A10 A11 NC

CY62147EV18 MoBL2

Product Portfolio

Power Dissipation

Product
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type
45 CY62147EV18LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array Pb-Free

Please contact your local Cypress sales representative for availability of other parts

Power Standby ISB Standby ISB Active ICC Active ICC

Active ICC

Active ICC Active ICC Active ICC Active ICC Active ICC

Active ICC

Operating Range

Industrial

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Package Diagram

TOP VIEW

A1 CORNER
12 3 4 5 6

A B C D E F G H

CY62147EV18 MoBL2
48-pin VFBGA 6 x 8 x 1 mm 51-85150

BOTTOM VIEW A1 CORNER

M C M C A B Ø0.30±0.05 48X
6 54 3 2 1

A B C D E F G H

B 0.15 4X

C MAX.

SEATING PLANE C
51-85150-*D

MAX.

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY62147EV18 MoBL2

Document History Page

Document Title:CY62147EV18 MoBL2 4-Mbit 256K x 16 Static RAM Document Number 38-05441

Orig. of ECN NO. Issue Date Change

Description of Change
201580 01/08/04

AJU New Data Sheet
247009 See ECN SYT Changed from Advance Information to Preliminary

Moved Product Portfolio to Page 2

Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages
414820 See ECN ZSD Changed from Preliminary to Final

Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”

Removed 35ns Speed Bin

Removed “L” version of CY62147EV18

Changed ball E3 from DNU to NC

Changed ICC Typ value from mA to 2 mA at f=1 MHz Changed ICC Max value from 2 mA to mA at f=1 MHz Changed ICC Typ value from 12 mA to 15 mA at f=fmax Changed ISB1 and ISB2 Typ. values from µA to 1 µA and Max. values from µA to 7 µA.

Extended undershoot limit to -2V in footnote #5

Changed ICCDR Max. from µA to 3 µA. Added ICCDR typical value. Changed tLZOE from 3 ns to 5 ns Changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns. Changed tSD from 22 ns to 25 ns. Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering information table and replaced Package Name column
with Package Diagram

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Datasheet ID: CY62147EV18LL-45BVXI 507817