CD4021BCM

CD4021BCM Datasheet

CD4021BC 8-Stage Static Shift Register

Part	Datasheet
CD4021BCM	CD4021BCM (pdf)

Related Parts	Information
CD4021BCMX	CD4021BCMX
CD4021BCN	CD4021BCN

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CD4021BC 8-Stage Static Shift Register CD4021BC 8-Stage Static Shift Register The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive. When the parallel/serial control input is in the logical “0” state, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/ serial control is in the logical “1” state, data is jammed into each stage of the register asynchronously with the clock. All inputs are protected against static discharge with diodes to VDD and VSS. s Wide supply voltage range 3.0V to 15V s High noise immunity VDD typ. s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full tempera- ture range Ordering Code: Order Number Order Code Package Description CD4021BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4021BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table CL Note 1 Serial Input Parallel/ Serial Control Q1 Internal Qn Note 2 X 0 1 X X = Don't care case Note 1 Level change Note 2 No change Qn−1 Qn−1 Qn Top View 2002 Fairchild Semiconductor Corporation DS005954 CD4021BC Logic Diagram CD4021BC Absolute Maximum Ratings Note 3 Note 4 Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL Soldering, 10 seconds −0.5V to +18V −0.5V to VDD +0.5V −65°C to +150°C 700 mW 500 mW 260°C Recommended Operating Conditions Note 4 Supply Voltage VDD Input Voltage VIN Operating Temperature Range TA CD4021BCN 3V to 15V 0 to VDD −55°C to +125°C Note 3 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 4 VSS = 0V unless otherwise specified. DC Electrical Characteristics Note 4 Parameter Conditions Quiescent Device VDD = 5V, VIN = VDD or VSS Current

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CD4021BC 8-Stage Static Shift Register

CD4021BC 8-Stage Static Shift Register

The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive.

When the parallel/serial control input is in the logical “0” state, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/ serial control is in the logical “1” state, data is jammed into each stage of the register asynchronously with the clock.

All inputs are protected against static discharge with diodes to VDD and VSS.
s Wide supply voltage range 3.0V to 15V s High noise immunity VDD typ. s Low power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LS s parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full tempera-
ture range
Ordering Code:

Order Number

Order Code

Package Description

CD4021BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4021BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

CL Note 1

Serial Input

Parallel/ Serial Control

Q1 Internal

Qn Note 2

X 0 1 X

X = Don't care case

Note 1 Level change

Note 2 No change

Qn−1 Qn−1 Qn

Top View
2002 Fairchild Semiconductor Corporation DS005954

CD4021BC

Logic Diagram

CD4021BC

Absolute Maximum Ratings Note 3

Note 4

Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD

Dual-In-Line

Small Outline

Lead Temperature TL Soldering, 10 seconds
−0.5V to +18V −0.5V to VDD +0.5V
−65°C to +150°C
700 mW 500 mW
260°C

Recommended Operating Conditions Note 4

Supply Voltage VDD Input Voltage VIN Operating Temperature Range TA

CD4021BCN
3V to 15V 0 to VDD
−55°C to +125°C

Note 3 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.

Note 4 VSS = 0V unless otherwise specified.

DC Electrical Characteristics Note 4

Parameter

Conditions

Quiescent Device

VDD = 5V, VIN = VDD or VSS

Current

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Datasheet ID: CD4021BCM 513560