CY7C1320JV18-250BZXI

CY7C1320JV18-250BZXI Datasheet


CY7C1318JV18 CY7C1320JV18

Part Datasheet
CY7C1320JV18-250BZXI CY7C1320JV18-250BZXI CY7C1320JV18-250BZXI (pdf)
Related Parts Information
CY7C1320JV18-300BZC CY7C1320JV18-300BZC CY7C1320JV18-300BZC
CY7C1318JV18-300BZC CY7C1318JV18-300BZC CY7C1318JV18-300BZC
CY7C1318JV18-300BZXC CY7C1318JV18-300BZXC CY7C1318JV18-300BZXC
CY7C1320JV18-300BZXC CY7C1320JV18-300BZXC CY7C1320JV18-300BZXC
PDF Datasheet Preview
CY7C1318JV18 CY7C1320JV18
18 Mbit DDR II SRAM Two Word Burst Architecture
• 18 Mbit Density 1M x 18, 512K x 36
• 300 MHz Clock for High Bandwidth
• Two word Burst for reducing Address Bus Frequency
• Double Data Rate DDR Interfaces data transferred at 600 MHz at 300 MHz
• Two Input Clocks K and K for Precise DDR Timing SRAM uses rising edges only
• Two Input Clocks for Output Data C and C to Minimize Clock Skew and Flight Time mismatches
• Echo Clocks CQ and CQ simplify Data Capture in High Speed systems
• Synchronous Internally self timed Writes
• DDR II Operates with Cycle Read Latency when the DLL is enabled
• Operates similar to a DDR I Device with 1 Cycle Read Latency in DLL Off Mode
• 1.8V Core Power Supply with HSTL Inputs and Outputs
• Variable drive HSTL Output Buffers
• Expanded HSTL Output Voltage
• Available in 165-ball FBGA Package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG Compatible Test Access Port
• Delay Lock Loop DLL for Accurate Data Placement

Configurations

CY7C1318JV18 1M x 18 CY7C1320JV18 512K x 36

Selection Guide

Maximum Operating Frequency

Maximum Operating Current

Functional Description

The CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a one bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. For CY7C1318JV18 and CY7C1320JV18, the burst counter takes in the least significant bit of the external address and bursts two 18 bit words in the case of CY7C1318JV18 of two 36 bit words in the case of CY7C1320JV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs, D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self timed write circuitry.
300 MHz 300 655 730
250 MHz 250 600 635

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
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CY7C1318JV18 CY7C1320JV18

Logic Block Diagram CY7C1318JV18

Burst

Logic

A 19:0 20 19 A 19:1

Address Register

Write Reg

Write Reg
512K x 18 Array 512K x 18 Array
Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
300 CY7C1318JV18-300BZC

CY7C1320JV18-300BZC

CY7C1318JV18-300BZXC

Package Diagram

Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1320JV18-300BZXC 250 CY7C1320JV18-250BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Industrial

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm
51-85180 *B

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CY7C1318JV18 CY7C1320JV18

Document History Page

Document Title CY7C1318JV18/CY7C1320JV18, 18 Mbit DDR II SRAM Two Word Burst Architecture Document Number 001-15271

Orig. of Change

Submission Date

Description of Change
** 1103944 VKN/KKVTMP See ECN New datasheet
*A 1423243 VKN/AESA See ECN Converted from preliminary to final Removed 250 MHz and 200 MHz Updated IDD/ISB specs Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed tCYC max spec to ns
*B 2189567 VKN/AESA See ECN Minor Change-Moved to the external web
*C 2521690 NXR/PYRS 06/26/08 Added 250 MHz speed bin Changed JTAG ID [31:29] from 001 to 000 Updated power up sequence waveform and its description Changed Ambient Temperature with Power Applied from to +85°C” to +125°C” in the “Maximum Ratings“ on page 20 Added footnote #19 related to IDD Changed ΘJA and ΘJC from and °C/W to and °C/W respectively
*D 2561974 VKN/PYRS 09/04/08 Corrected typo in the CY7C1318JV18’s pinout
*E 2755901
08/25/09
Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Updated Package Diagram.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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More datasheets: 100LVELT22M | 10828F | FQPF6N60 | AD608AR-REEL7 | EPCDESIGNTOOL_XL-EM | AFBR-703SDZ | CY7C1320JV18-300BZC | CY7C1318JV18-300BZC | CY7C1318JV18-300BZXC | CY7C1320JV18-300BZXC


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Datasheet ID: CY7C1320JV18-250BZXI 507961