CD4011BCMX
CD4011BCMX Datasheet
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate<br>• Quad 2-Input NAND Buffered B Series Gate
| Part | Datasheet |
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CD4011BCMX |
CD4011BCMX (pdf) |
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| CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate The CD4001BC and CD4011BC quad gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS. s Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS s parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full temperature range Ordering Code: Order Number Package Number Package Description CD4001BCM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4001BCSJ M14D 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide CD4011BCM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC and SOP CD4001BC Pin Assignments for DIP and SOIC CD4011BC Top View 2002 Fairchild Semiconductor Corporation DS005939 Top View CD4001BC/CD4011BC Schematic Diagrams CD4001BC 1/4 of device shown J=A+B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. CD4011BC 1/4 of device shown J=A•B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. CD4001BC/CD4011BC Absolute Maximum Ratings Note 1 Note 2 Voltage at any Pin Power Dissipation PD Dual-In-Line Small Outline VDD Range Storage Temperature TS Lead Temperature TL Soldering, 10 seconds −0.5V to VDD +0.5V 700 mW 500 mW VDC to +18 VDC −65°C to +150°C 260°C Recommended Operating Conditions Operating Range VDD Operating Temperature Range 3 VDC to 15 VDC CD4001BC, CD4011BC −55°C to +125°C Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics tables provide conditions for actual device operation. Note 2 All voltages measured with respect to VSS unless otherwise specified. DC Electrical Characteristics Note 2 Parameter Conditions Quiescent Device VDD = 5V, VIN = VDD or VSS Current VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS LOW Level VDD = 5V Output Voltage VDD = 10V |IO| < 1 µA VDD = 15V HIGH Level VDD = 5V |
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