74LVX112MTC

74LVX112MTC Datasheet

74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear

Part	Datasheet
74LVX112MTC	74LVX112MTC (pdf)

Related Parts	Information
74LVX112MTCX	74LVX112MTCX
74LVX112SJ	74LVX112SJ
74LVX112SJX	74LVX112SJX
74LVX112MX	74LVX112MX
74LVX112M	74LVX112M

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74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs Q, Q . These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. Clear and Preset are independent of the clock and are accomplished by a low logic level on the corresponding input. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. s Input voltage level translation from s Ideal for low power/low noise 3.3V applications Ordering Code: Order Number Package Number Package Description 74LVX112M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74LVX112SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74LVX112MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names J1, J2, K1, K2 CLK1, CLK2 CLR1, CLR2 PR1, PR2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs Active Falling edge Direct Clear Inputs Active LOW Direct Preset Inputs Active LOW 2003 Fairchild Semiconductor Corporation DS012158 74LVX112 Truth Table Inputs Outputs PR CLR CP J K Q X XX H L X XX L H X XX H H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = HIGH-to-LOW Clock Transition Q0 = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram One Half Shown 74LVX112 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current ICC or IGND Storage Temperature TSTG Power Dissipation −0.5V to +7.0V −20 mA −0.5V to 7V −20 mA +20 mA −0.5V to VCC + 0.5V ±25 mA ±50 mA −65°C to +150°C 180 mW Recommended Operating Conditions Note 2 Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Input Rise and Fall Time 2.0V to 3.6V 0V to 5.5V 0V to VCC −40°C to +85°C 0 ns/V to 100 ns/V Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2 Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Parameter

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74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear
74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear

The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs Q, Q . These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. Clear and Preset are independent of the clock and are accomplished by a low logic level on the corresponding input. The J and K inputs can change when the clock is in
either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.
s Input voltage level translation from s Ideal for low power/low noise 3.3V applications
Ordering Code:

Order Number Package Number

Package Description
74LVX112M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74LVX112SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74LVX112MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

J1, J2, K1, K2 CLK1, CLK2 CLR1, CLR2 PR1, PR2 Q1, Q2, Q1, Q2

Data Inputs Clock Pulse Inputs Active Falling edge Direct Clear Inputs Active LOW Direct Preset Inputs Active LOW
2003 Fairchild Semiconductor Corporation DS012158
74LVX112

Truth Table

Inputs

Outputs

PR CLR CP J K Q

X XX H L

X XX L H

X XX H

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = HIGH-to-LOW Clock Transition Q0 = Before HIGH-to-LOW Transition of Clock

Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.

Logic Diagram

One Half Shown
74LVX112

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V DC Input Voltage VI DC Output Diode Current IOK

VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current

ICC or IGND Storage Temperature TSTG Power Dissipation
−0.5V to +7.0V
−20 mA −0.5V to 7V
−20 mA +20 mA −0.5V to VCC + 0.5V
±25 mA
±50 mA −65°C to +150°C
180 mW

Recommended Operating Conditions Note 2

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Input Rise and Fall Time
2.0V to 3.6V 0V to 5.5V 0V to VCC
−40°C to +85°C 0 ns/V to 100 ns/V

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2 Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Parameter

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Datasheet ID: 74LVX112MTC 513444