74LVTH16543MTD

74LVTH16543MTD Datasheet

74LVT16543<br>• 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

Part	Datasheet
74LVTH16543MTD	74LVTH16543MTD (pdf)

Related Parts	Information
74LVTH16543MTDX	74LVTH16543MTDX
74LVTH16543MEA	74LVTH16543MEA
74LVTH16543MEAX	74LVTH16543MEAX

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74LVT16543 • 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs 74LVT16543 • 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs The LVT16543 and LVTH16543 16-bit transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation. The LVTH16543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These transceivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16543 and LVTH16543 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH16543 s Also available without bushold feature 74LVT16543 s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16543 s Latch-up conforms to JEDEC JED78 s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVT16543MEA Preliminary MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74LVT16543MTD Preliminary MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide 74LVTH16543MEA MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74LVTH16543MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol 2001 Fairchild Semiconductor Corporation DS012449 74LVT16543 • 74LVTH16543 Connection Diagram Pin Descriptions Pin Names OEABn OEBAn CEABn CEBAn LEABn LEBAn A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs Functional Description The LVT16543 and LVTH16543 contain two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable CEAB input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/ O Control Table. With CEAB LOW, a low signal on LEAB input makes the A to B latches transparent a subsequent LOW-to-HIGH transition of the LEAB line puts the Data I/O Control Table A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate control inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver. CEABn Inputs LEABn OEABn Latch Status Byte n Latched Latched Transparent H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn Output Buffers Byte n High Z High Z Driving 74LVT16543 • 74LVTH16543 Logic Diagrams Byte 1 0:7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Byte 2 8:15 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVT16543 • 74LVTH16543 Absolute Maximum Ratings Note 1 VCC VI VO Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value to −50 −50 64 128 ±64 ±128 −65 to +150

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74LVT16543
• 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
74LVT16543
• 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

The LVT16543 and LVTH16543 16-bit transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation.

The LVTH16543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These transceivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16543 and LVTH16543 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH16543
s Also available without bushold feature 74LVT16543 s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16543 s Latch-up conforms to JEDEC JED78 s ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:

Order Number Package Number

Package Description
74LVT16543MEA Preliminary

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74LVT16543MTD Preliminary

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
74LVTH16543MEA

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74LVTH16543MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol
2001 Fairchild Semiconductor Corporation DS012449
74LVT16543
• 74LVTH16543

Connection Diagram

Pin Descriptions

Pin Names

OEABn OEBAn CEABn CEBAn LEABn LEBAn

A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs

Functional Description

The LVT16543 and LVTH16543 contain two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable CEAB input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/ O Control Table. With CEAB LOW, a low signal on LEAB input makes the A to B latches transparent a subsequent LOW-to-HIGH transition of the LEAB line puts the

Data I/O Control Table

A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate control inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver.

CEABn

Inputs LEABn

OEABn

Latch Status Byte n

Latched

Latched

Transparent

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn

Output Buffers Byte n

High Z

High Z Driving
74LVT16543
• 74LVTH16543

Logic Diagrams

Byte 1 0:7

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Byte 2 8:15

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVT16543
• 74LVTH16543

Absolute Maximum Ratings Note 1

VCC VI VO

Parameter Supply Voltage DC Input Voltage DC Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Current

ICC IGND TSTG

DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Value to
−50 −50 64 128 ±64 ±128 −65 to +150

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Datasheet ID: 74LVTH16543MTD 513434