FMS7401LVN14

FMS7401LVN14 Datasheet

FMS7401L

Part	Datasheet
FMS7401LVN14	FMS7401LVN14 (pdf)

Related Parts	Information
FMS7401LEN14	FMS7401LEN14
FMS7401LEN	FMS7401LEN
FMS7401LVN	FMS7401LVN

PDF Datasheet Preview
FMS7401L Digital Power Controller The FMS7401L is a Digital Power Controller designed for applications requiring ease of digital based control over analog based implementations. The FMS7401L is an ideal solution to implement ballast control, motor control and battery management functions. It integrates a wide variety of analog blocks with an 8-bit microcontroller core to offer a complementary feature set with high performance, low power and small size in a single chip. The FMS7401L is intended for applications using a supply voltage in the 2.7V to 3.6V range. It is fabricated using CMOS technology and is fully static offering a power savings. The FMS7401L is available in both 8-pin and 14-pin PDIP, SOIC and TSSOP packages. • 8-bit Microcontroller Core • 1K bytes on-board code EEPROM • 64 bytes data EEPROM • 64 bytes SRAM • Watchdog Reset • Multi-input Wakeup on all general purpose I/O pins • Fast 12-bit PWM timer with dead time control and half- bridge output drive Input Capture Mode • 5-Ch 8-bit Analog-to-Digital Converter 20 µS conversion time Sample and Hold Internal Voltage Reference 1.21V Gated Auto-sampling Mode • Auto-zero gain 16 • Uncommitted • Internal Current Source Generator 1mA • On-chip Oscillator No external components 1µs instruction cycle time • On-chip Power-on Reset • Programmable read and write disable functions • Memory Mapped I/O • Programmable Comparator 63 Levels • Brown-out Reset • Software selectable I/O option • Push-pull outputs with tri-state option • Weak pull-up or high impedance inputs • Fully static CMOS Power Saving Halt Mode < 1.3µA 3.3V Power Saving Idle Mode < 180µA 3.3V • Single supply operation 2.7V 3.6V • 40 years data retention • 100,000 data changes • 8-/14-pin PDIP, SOIC, and TSSOP packages • In-circuit programming Fast Page-write Programming Mode Program Data Memory bytes Device Supply Voltage Memory bytes SRAM Data EEPROM FMS7401L 2.7V 3.6V FMS7401L 2.7V 3.6V Pin Count 8 14 FMS7401L Block Diagram RESET G7/AIN4/ AOUT G6/-AIN G3/AIN1 G2/AIN2 G1/AIN3/ ADSTROBE SR_GND G4/AIN0 NC/GND VREF Uncommitted Amplifier AOUT Analog ACH5 ACH2 ACH3 Y S/H ACH4 8-bit ADC Autozero Amplifier _ Ordering Information 77 Physical Dimensions 78 FMS7401L PRODUCT SPECIFICATION List of Figures Figure FMS7401L Block and Connection Diagram 2 BOR and POR Circuit Relationship Diagram 9 Internal Clock Scheme 11 External Clock Scheme 12 Recommended Halt/Idle Flow 13 ADC Block Diagram 17 Current Generator Interface 24 Programmable Comparator Block Diagram VLOOP = 0 26 Programmable Comparator Block Diagram VLOOP = 1 29 Digital Delay Timing 31 Timer 1’s PWM Mode Block Diagram 39 Example PWM Output Signals a and b 39 Timer 1’s Input Capture Mode Block Diagram 40 PORTGD Logic Diagram 43 Multi-input Wakeup MIW Block Diagram 45 Core Program Model 46 Basic Interrupt Structure 49 Programming Mode Pin 59 Programming Protocol 62 Serial Data Timing 62 Page Mode Protocol 62 Internal Oscillator Frequency FOSC vs. Temperature 68 Icc Active vs. Temperature no PLL or data EEPROM writes 68 Icc Active vs. Temperature no PLL, with data EEPROM writes 69 Icc Active vs. Temperature with PLL, no data EEPROM writes 69 Halt Current vs. Temperature 70 Idle Current vs. Temperature no PLL 70 Idle Current vs. Temperature with PLL 71 VOL vs. IOL 25°C G6, G7 71 VOL vs. IOL 25°C G0, G5 72 VOH vs. IOH 25°C G6, G7 72 VOH vs. IOH 25°C G0, G5 73 BOR Level vs. Temperature 73 Programmable Comparator Voltage Level vs. Temperature 74 VREF vs. Temperature 74 Current Source ISRC vs. Temperature 75 Gain 16 Error vs. Temperature 75 PRODUCT SPECIFICATION FMS7401L List of Tables Table Default Register States 8 CMODE Bit 10 PLL Frequency Selection FPLL/FOSC = 2MHz 10 HALT Register 13 ADCNTRL1 Register Bit 19 Analog Input Channel Selection ACHSEL[3:0] Bit 19 ADCNTRL2 Register Bit 21 Programmable Comparator COMP Control Register Bit 25 Programmable Comparator Lower Voltage Reference VTHL Levels 1 31 27 Programmable Comparator Upper Voltage Reference VTHU Levels 32 63 28 Digital Delay DDELAY Register Bit 31 Prescale PSCALE Register Bit 33 PLL Divide Factor Selection Bits and the FT1CLK Resolution FOSC=2 MHz 33 Timer 1 Prescale Selection PS Bits 34 Dead Time DTIME Register Bit 35 Timer 1 Control T1CNTRL Register Bit 37 Timer 1 Mode Bits 37 Timer 0 Control T0CNTRL Register 41 Watchdog Service Register WDSVR 42 I/O Register Bit Assignments 43 I/O Options 43 Multi-input Wakeup MIW Register Bit Assignments 45 Interrupt Priority Sequence 48 Instruction Addressing Modes 51 Instruction Cycles and Bytes 52 Initialization Register 1 Bit 55 Initialization Register 3 Bit 55 Initialization Register 4 Bit 55 T1HS1 G0 and T1HS2 G5 Default 56 Memory Mapped Registers 57 Memory Mapped Registers and their Register Bit 58 Programming Interface Electrical Characteristics 59 32-Bit Command and Response Word 61 FMS7401L PRODUCT SPECIFICATION 1 Reset Circuit The reset circuit in the FMS7401L contains four input conditions that trigger a main system reset. When the main system reset is triggered, a sequence of events occur defaulting all memory mapped registers including the initialization registers and I/Os to their initial states see Table During the system reset sequence, the instruction core execution is halted allowing time for the internal oscillator and other analog circuits to stabilize. Once the system reset sequence completes, the device will begin with its normal operation executing the instruction program residing in the code EEPROM memory. The time required for the system reset sequence to complete TRESET is dependent on the individual trigger condition and is in the Electrical Characteristics section of the datasheet. The four reset trigger conditions are as follows: • Power-on Reset POR • External Reset1 • Brown-out Reset BOR • Watchdog Reset2 Table Default Register States Peripheral/Register G1, G2, G3, G4, G6, G7 G0, G5 SRAM Memory Stack Pointer Status Register T1CMPA, T1CMPB and T1RA Registers DTIME Register All other memory mapped register not listed above.3 External Reset High-impedance input tri-state input by Init Reg. 4 see Table 28 No change 0x80 0x80 0xFFF 0xFFF 0x1F 0x1F 0x00 0x00 Power-on Reset Circuit The Power-on Reset POR circuit maintains the device in a reset state until Vcc reaches a voltage level high enough to guarantee proper device operation. The POR circuit is sensitive to the different Vcc ramp rates and must be within SVcc as in the Electrical Characteristics section of the datasheet. The POR circuit does not generate a system reset when Vcc is falling. This feature is performed by the Brown-out Reset BOR circuit and must be enabled by the BOREN bit of the Initialization Register In the case where Vcc does not drop to 0V before the next power-up sequence, it is necessary to enable the BOR circuit and/or reset the device externally through the RESET pin.1 External Reset1 The device may be externally reset through the RESET input pin if the POR/BOR circuits cannot be used to properly reset the device in the application. The RESET input pin contains an internal pull-up resistor making it an active low signal. Therefore, to issue a device system reset the RESET input should be held low for at least 10µS before being released i.e. returned to a high state . While the RESET input is held low, the internal oscillator and other analog circuits are kept in a low power state reducing the current consumption of the device a state resembling Halt Mode . In addition, the I/O pins are all initialized to an input tri-state unless defaulted otherwise.5 At the rising edge of the RESET input signal, the main system reset sequence is triggered releasing the internal oscillator and other analog circuits so that they may be initialized and begin their normal operation. Brown-out Reset Circuit The Brown-out Reset BOR circuit is one of the on-chip analog comparator peripherals and must be enabled through the BOREN bit of the Initialization Registers The BOR circuit is used to hold the device in a reset state when Vcc drops below a threshold in the Electrical Characteristics section of the datasheet. While in reset, the device is held in its initial condition until Vcc rises above the threshold. Shortly after Vcc rises above the threshold, the internal system reset sequence is started. Once the system reset sequence completes, the device will begin with its normal operation executing the instruction program residing in the code EEPROM memory. PRODUCT SPECIFICATION FMS7401L Ordering Information FSID FMS7401LEN FMS7401LVN FMS7401LEN14 FMS7401LVN14 FMS7401LEM8X FMS7401LEMX FMS7401LEMT8X FMS7401LEMTX Package PDIP8 PDIP14 SOIC8 SOIC14 TSSOP8 TSSOP14 Supply Voltage 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V Temperature Range -40°C to 85°C -40°C to 125°C -40°C to 85°C -40°C to 125°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C PRODUCT SPECIFICATION Packaging Option Method Rail Rail Rail Rail Tape Reel 2500 Tape Reel 2500 Tape Reel 2500 Tape Reel 2500 PRODUCT SPECIFICATION Physical Dimensions†† 8-Pin PDIP 14-Pin PDIP 95° ±5 DIA Pin #1 IDENT 8765 Option 1 1234 Typ. MAX 20° ±1° Pin #1 IDENT 1 Option 2 DIA NOM 90° 4° Typ FMS7401L 14 13 12 11 10 9 8 PIN NO. 1 IDENT 1 23 4 5 67 MAX DEPTH OPTION 1

PDF Datasheet Preview

FMS7401L

Digital Power Controller

The FMS7401L is a Digital Power Controller designed for applications requiring ease of digital based control over analog based implementations. The FMS7401L is an ideal solution to implement ballast control, motor control and battery management functions. It integrates a wide variety of analog blocks with an 8-bit microcontroller core to offer a complementary feature set with high performance, low power and small size in a single chip.

The FMS7401L is intended for applications using a supply voltage in the 2.7V to 3.6V range. It is fabricated using CMOS technology and is fully static offering a power savings. The FMS7401L is available in both 8-pin and 14-pin PDIP, SOIC and TSSOP packages.
• 8-bit Microcontroller Core
• 1K bytes on-board code EEPROM
• 64 bytes data EEPROM
• 64 bytes SRAM
• Watchdog Reset
• Multi-input Wakeup on all general purpose I/O pins
• Fast 12-bit PWM timer with dead time control and half-
bridge output drive Input Capture Mode
• 5-Ch 8-bit Analog-to-Digital Converter 20 µS conversion time Sample and Hold Internal Voltage Reference 1.21V Gated Auto-sampling Mode
• Auto-zero gain 16
• Uncommitted
• Internal Current Source Generator 1mA
• On-chip Oscillator

No external components 1µs instruction cycle time
• On-chip Power-on Reset
• Programmable read and write disable functions
• Memory Mapped I/O
• Programmable Comparator 63 Levels
• Brown-out Reset
• Software selectable I/O option
• Push-pull outputs with tri-state option
• Weak pull-up or high impedance inputs
• Fully static CMOS Power Saving Halt Mode
< 1.3µA 3.3V Power Saving Idle Mode
< 180µA 3.3V
• Single supply operation
2.7V 3.6V
• 40 years data retention
• 100,000 data changes
• 8-/14-pin PDIP, SOIC, and TSSOP packages
• In-circuit programming

Fast Page-write Programming Mode

Program

Data Memory bytes

Device

Supply Voltage Memory bytes

SRAM

Data EEPROM

FMS7401L
2.7V 3.6V

FMS7401L
2.7V 3.6V

Pin Count 8 14

FMS7401L

Block Diagram

RESET

G7/AIN4/ AOUT

G6/-AIN

G3/AIN1 G2/AIN2 G1/AIN3/ ADSTROBE

SR_GND G4/AIN0

NC/GND

VREF

Uncommitted Amplifier

AOUT

Analog

ACH5

ACH2

ACH3 Y S/H

ACH4
8-bit ADC

Autozero Amplifier _
Ordering Information 77

Physical Dimensions 78

FMS7401L

PRODUCT SPECIFICATION

List of Figures

Figure

FMS7401L Block and Connection Diagram 2 BOR and POR Circuit Relationship Diagram 9 Internal Clock Scheme 11 External Clock Scheme 12 Recommended Halt/Idle Flow 13 ADC Block Diagram 17 Current Generator Interface 24 Programmable Comparator Block Diagram VLOOP = 0 26 Programmable Comparator Block Diagram VLOOP = 1 29 Digital Delay Timing 31 Timer 1’s PWM Mode Block Diagram 39 Example PWM Output Signals a and b 39 Timer 1’s Input Capture Mode Block Diagram 40 PORTGD Logic Diagram 43 Multi-input Wakeup MIW Block Diagram 45 Core Program Model 46 Basic Interrupt Structure 49 Programming Mode Pin 59 Programming Protocol 62 Serial Data Timing 62 Page Mode Protocol 62 Internal Oscillator Frequency FOSC vs. Temperature 68 Icc Active vs. Temperature no PLL or data EEPROM writes 68 Icc Active vs. Temperature no PLL, with data EEPROM writes 69 Icc Active vs. Temperature with PLL, no data EEPROM writes 69 Halt Current vs. Temperature 70 Idle Current vs. Temperature no PLL 70 Idle Current vs. Temperature with PLL 71 VOL vs. IOL 25°C G6, G7 71 VOL vs. IOL 25°C G0, G5 72 VOH vs. IOH 25°C G6, G7 72 VOH vs. IOH 25°C G0, G5 73 BOR Level vs. Temperature 73 Programmable Comparator Voltage Level vs. Temperature 74 VREF vs. Temperature 74 Current Source ISRC vs. Temperature 75 Gain 16 Error vs. Temperature 75

PRODUCT SPECIFICATION

FMS7401L

List of Tables

Table

Default Register States 8 CMODE Bit 10 PLL Frequency Selection FPLL/FOSC = 2MHz 10 HALT Register 13 ADCNTRL1 Register Bit 19 Analog Input Channel Selection ACHSEL[3:0] Bit 19 ADCNTRL2 Register Bit 21 Programmable Comparator COMP Control Register Bit 25 Programmable Comparator Lower Voltage Reference VTHL Levels 1 31 27 Programmable Comparator Upper Voltage Reference VTHU Levels 32 63 28 Digital Delay DDELAY Register Bit 31 Prescale PSCALE Register Bit 33 PLL Divide Factor Selection Bits and the FT1CLK Resolution FOSC=2 MHz 33 Timer 1 Prescale Selection PS Bits 34 Dead Time DTIME Register Bit 35 Timer 1 Control T1CNTRL Register Bit 37 Timer 1 Mode Bits 37 Timer 0 Control T0CNTRL Register 41 Watchdog Service Register WDSVR 42 I/O Register Bit Assignments 43 I/O Options 43 Multi-input Wakeup MIW Register Bit Assignments 45 Interrupt Priority Sequence 48 Instruction Addressing Modes 51 Instruction Cycles and Bytes 52 Initialization Register 1 Bit 55 Initialization Register 3 Bit 55 Initialization Register 4 Bit 55 T1HS1 G0 and T1HS2 G5 Default 56 Memory Mapped Registers 57 Memory Mapped Registers and their Register Bit 58 Programming Interface Electrical Characteristics 59 32-Bit Command and Response Word 61

FMS7401L

PRODUCT SPECIFICATION
1 Reset Circuit

The reset circuit in the FMS7401L contains four input conditions that trigger a main system reset. When the main system reset is triggered, a sequence of events occur defaulting all memory mapped registers including the initialization registers and I/Os to their initial states see Table During the system reset sequence, the instruction core execution is halted allowing time for the internal oscillator and other analog circuits to stabilize. Once the system reset sequence completes, the device will begin with its normal operation executing the instruction program residing in the code EEPROM memory. The time required for the system reset sequence to complete TRESET is dependent on the individual trigger condition and is in the Electrical Characteristics section of the datasheet. The four reset trigger conditions are as follows:
• Power-on Reset POR
• External Reset1
• Brown-out Reset BOR
• Watchdog Reset2

Table Default Register States

Peripheral/Register G1, G2, G3, G4, G6, G7 G0, G5 SRAM Memory Stack Pointer Status Register T1CMPA, T1CMPB and T1RA Registers DTIME Register All other memory mapped register not listed above.3

External Reset

High-impedance input tri-state input
by Init Reg. 4 see Table 28

No change
0x80
0x80
0xFFF
0xFFF
0x1F
0x1F
0x00
0x00

Power-on Reset Circuit

The Power-on Reset POR circuit maintains the device in a reset state until Vcc reaches a voltage level high enough to guarantee proper device operation. The POR circuit is sensitive to the different Vcc ramp rates and must be within SVcc as in the Electrical Characteristics section of the datasheet.

The POR circuit does not generate a system reset when Vcc is falling. This feature is performed by the Brown-out Reset BOR circuit and must be enabled by the BOREN bit of the Initialization Register In the case where Vcc does not drop to 0V
before the next power-up sequence, it is necessary to enable the BOR circuit and/or reset the device externally through the RESET pin.1

External Reset1

The device may be externally reset through the RESET input pin if the POR/BOR circuits cannot be used to properly reset the device in the application. The RESET input pin contains an internal pull-up resistor making it an active low signal. Therefore, to issue a device system reset the RESET input should be held low for at least 10µS before being released i.e. returned to a high state . While the RESET input is held low, the internal oscillator and other analog circuits are kept in a low power state reducing the current consumption of the device a state resembling Halt Mode . In addition, the I/O pins are all initialized to an input tri-state unless defaulted otherwise.5 At the rising edge of the RESET input signal, the main system reset sequence is triggered releasing the internal oscillator and other analog circuits so that they may be initialized and begin their normal operation.

Brown-out Reset Circuit

The Brown-out Reset BOR circuit is one of the on-chip analog comparator peripherals and must be enabled through the BOREN bit of the Initialization Registers The BOR circuit is used to hold the device in a reset state when Vcc drops below a threshold in the Electrical Characteristics section of the datasheet. While in reset, the device is held in its initial condition until Vcc rises above the threshold. Shortly after Vcc rises above the threshold, the internal system reset sequence is started. Once the system reset sequence completes, the device will begin with its normal operation executing the instruction program residing in the code EEPROM memory.

PRODUCT SPECIFICATION

FMS7401L
Ordering Information

FSID FMS7401LEN FMS7401LVN FMS7401LEN14 FMS7401LVN14 FMS7401LEM8X FMS7401LEMX FMS7401LEMT8X FMS7401LEMTX

Package PDIP8 PDIP14 SOIC8 SOIC14

TSSOP8 TSSOP14

Supply Voltage 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V

Temperature Range -40°C to 85°C -40°C to 125°C -40°C to 85°C -40°C to 125°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C

PRODUCT SPECIFICATION

Packaging Option

Method

Rail

Rail

Rail

Rail

Tape Reel
2500

Tape Reel
2500

Tape Reel
2500

Tape Reel
2500

PRODUCT SPECIFICATION

Physical Dimensions††
8-Pin PDIP
14-Pin PDIP
95° ±5

DIA Pin #1 IDENT
8765

Option 1
1234

Typ. MAX 20° ±1°

Pin #1 IDENT
1 Option 2

DIA NOM
90° 4° Typ

FMS7401L
14 13 12 11 10 9 8

PIN NO. 1 IDENT
1 23 4 5 67

MAX DEPTH

OPTION 1

More datasheets: 17801-S30 | 1020B5743-05 | 1020B5743-04 | 1020B5743-03 | 1020B5743-02 | 1020B5743-01 | SSF212X050 | SSF212XP | FMS7401LEN14 | FMS7401LEN

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Datasheet ID: FMS7401LVN14 514940