74LVTH32374GX

74LVTH32374GX Datasheet

74LVT32374<br>• 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74LVTH32374GX	74LVTH32374GX (pdf)

PDF Datasheet Preview
74LVT32374 • 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs 74LVT32374 • 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs The LVT32374 and LVTH32374 contain thirty-two noninverting D-type flip-flops with 3-STATE outputs and are intended for bus oriented applications. The device is byte controlled. A buffered clock CP and Output Enable OE are common to each byte and can be shorted together for full 32-bit operation. The LVTH32374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These flip-flops are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32374 and LVTH32374 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH32374 s Also available without bushold feature 74LVT32374 s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array FBGA Ordering Code: Order Number Package Number Package Description 74LVT32374G Note 1 Note 2 BGA96A 96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Preliminary 74LVTH32374G Note 1 Note 2 BGA96A 96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Note 1 Ordering code “G” indicates Trays. Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol 2002 Fairchild Semiconductor Corporation DS500452 74LVT32374 • 74LVTH32374 Connection Diagram Pin Descriptions Pin Names OEn CPn Output Enable Input Active LOW Clock Pulse Input Inputs 3-STATE Outputs FBGA Pin Assignments Top Thru View O0 OE1 CP1 O2 GND I2 O4 VCC1 O6 GND I6 O8 GND I8 O10 VCC1 O13 O12 GND I12 O14 O15 OE2 CP2 O17 O16 OE3 CP3 O19 O18 GND I18 O20 VCC2 O23 O22 GND I22 O25 O24 GND I24 O26 VCC2 O29 O28 GND I28 O30 O31 OE4 CP4 Functional Description The LVT32374 and LVTH32374 consist of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Truth Tables Inputs OE1 L Outputs H L Oo Z Inputs OE2 L Outputs H L Oo Z Inputs OE3 L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

PDF Datasheet Preview

74LVT32374
• 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs
74LVT32374
• 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs

The LVT32374 and LVTH32374 contain thirty-two noninverting D-type flip-flops with 3-STATE outputs and are intended for bus oriented applications. The device is byte controlled. A buffered clock CP and Output Enable OE are common to each byte and can be shorted together for full 32-bit operation.

The LVTH32374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These flip-flops are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32374 and LVTH32374 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH32374
s Also available without bushold feature 74LVT32374 s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink −32 mA/+64 mA s ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array FBGA
Ordering Code:

Order Number

Package Number

Package Description
74LVT32374G Note 1 Note 2

BGA96A 96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Preliminary
74LVTH32374G Note 1 Note 2

BGA96A 96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
Note 1 Ordering code “G” indicates Trays.
Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol
2002 Fairchild Semiconductor Corporation DS500452
74LVT32374
• 74LVTH32374

Connection Diagram

Pin Descriptions

Pin Names

OEn CPn

Output Enable Input Active LOW Clock Pulse Input Inputs 3-STATE Outputs

FBGA Pin Assignments

Top Thru View

O0 OE1 CP1

O2 GND I2

O4 VCC1

O6 GND I6

O8 GND I8

O10 VCC1

O13 O12 GND I12

O14 O15 OE2 CP2

O17 O16 OE3 CP3

O19 O18 GND I18

O20 VCC2

O23 O22 GND I22

O25 O24 GND I24

O26 VCC2

O29 O28 GND I28

O30 O31 OE4 CP4

Functional Description

The LVT32374 and LVTH32374 consist of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.

Truth Tables

Inputs

OE1 L

Outputs

H L Oo Z

Inputs

OE2 L

Outputs

H L Oo Z

Inputs

OE3 L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74LVTH32374GX Datasheet file may be downloaded here without warranties.

Datasheet ID: 74LVTH32374GX 513429