CS42L55-CNZ

CS42L55-CNZ Datasheet


CS42L55

Part Datasheet
CS42L55-CNZ CS42L55-CNZ CS42L55-CNZ (pdf)
Related Parts Information
CS42L55-CNZR CS42L55-CNZR CS42L55-CNZR
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CS42L55

Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

DIGITAL to ANALOG FEATURES
5 mW Stereo Playback Power Consumption 99 dB Dynamic Range A-wtd -86 dB THD+N Digital Signal Processing Engine

Bass & Treble Tone Control, De-Emphasis Master Volume Control +12 to -102 dB in
dB steps Soft-Ramp & Zero-Cross Transitions Programmable Peak-Detect and Limiter Beep Generator w/Full Tone Control

Stereo Headphone and Line Amplifiers

Step-Down/Inverting Charge Pump Class H Amplifier - Automatic Supply Adj.

High Efficiency Low EMI Pseudo-Differential Ground-Centered Outputs High HP Power Output at -75 dB THD+N 2 x 20 mW Into 32 Ω V 2 x 20 mW Into 16 Ω V 1 VRMS Line Output V Analog Vol. Ctl. +12 to -55 dB in 1 dB steps Analog In to Analog Out Passthrough Pop and Click Suppression

ANALOG to DIGITAL FEATURES
mW Stereo Record Power Consumption 95 dB Dynamic Range A-wtd -87 dB THD+N 2:1 Stereo Input MUX Analog Programmable Gain Amplifier PGA
+12 to -6 dB in dB steps
+20 dB Boost Programmable Automatic Level Control ALC

Noise Gate for Noise Suppression Programmable Threshold &

Attack/Release Rates Independent ADC Channel Control Digital Vol. Ctl. 0 to -96 dB in 1 dB steps High-Pass Filter Disable for DC Measurements Pseudo Differential Inputs

SYSTEM FEATURES
12 MHz USB Master Clock Input Low Power Operation

Stereo Anlg. Passthrough mW V Stereo Rec. and Playback mW V Headphone Detect Input

SYSTEM FEATURES continued on page 2

V to V Analog/Digital Supply

LDO Regulator

V to V Charge Pump Supply

Step-Down

Inverting

Left 1

Pseudo Diff. Input

Right 1

Left 2

Pseudo Diff. Input

Right 2

Multi-bit

Attenuator, Boost, Mix

Beep

Mono mix, Limiter, Bass, Treble Adjust

Multi-bit

Control Port Serial Audio Port Level Shifter
+VHP
-VHP

Ground-Centered Amplifiers

Left HP Output

Pseudo Diff. Input
The CS42L55 is available in a 36-pin QFN package for the Commercial -40°C to +85°C grade. The CDB42L55 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 73 for complete details.

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TABLE OF CONTENTS

PIN DESCRIPTIONS 8 I/O Pin Characteristics 9

TYPICAL CONNECTION DIAGRAM 10 CHARACTERISTIC AND SPECIFICATION TABLES 11

RECOMMENDED OPERATING CONDITIONS 11 ABSOLUTE MAXIMUM RATINGS 11 ANALOG INPUT CHARACTERISTICS 12 ADC DIGITAL FILTER CHARACTERISTICS 13 HP OUTPUT CHARACTERISTICS 14 LINE OUTPUT CHARACTERISTICS 15 ANALOG PASSTHROUGH CHARACTERISTICS 16 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE 16 SWITCHING SPECIFICATIONS - SERIAL PORT 17 SWITCHING SPECIFICATIONS - CONTROL PORT 18 POWER SUPPLY REJECTION PSRR CHARACTERISTICS 19 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS 19 POWER CONSUMPTION - ALL SUPPLIES = V 20 POWER CONSUMPTION - ALL SUPPLIES = V 21 APPLICATIONS 22 Overview 22

Basic Architecture 22 Line Inputs 22 Line and Headphone Outputs Class H, Ground-Centered Amplifiers 22 Fixed-Function DSP Engine 22 Beep Generator 22 Power Management 22 Analog Inputs 23 Pseudo-Differential Inputs 24 Automatic Level Control ALC 24 Analog In to Analog Out Passthrough 25 Analog Outputs 26 Class H Amplifier 27 Power Control Options 27

Standard Class AB Operation Mode 01 and 10 28 Adapted to Volume Settings Mode 00 28 Adapted to Output Signal Mode 11 29 Power Supply Transitions 29 Efficiency 31 Beep Generator 31 Limiter 32 Serial Port Clocking 34 Digital Interface Format 34 Initialization 34 Recommended DAC to HP or Line Power-Up Sequence Playback 35 Recommended Power-Down Sequence 36 Recommended PGA to HP or Line Power-Up Sequence Analog Passthrough 36 Recommended Power-Down Sequence 36 Required Initialization Settings 37 Control Port Operation 38 Control 38 Memory Address Pointer MAP 39 Map Increment INCR 39

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REGISTER QUICK REFERENCE 40 REGISTER DESCRIPTION 42

Power Control 1 Address 02h 42 Power Down ADC Charge Pump 42 Power Down ADC x 42 Power Down 42

Power Control 2 Address 03h 43 Headphone Power Control 43 Line Power Control 43

Clocking Control 1 Address 04h 43 Master/Slave Mode 43 SCLK Polarity 43 SCLK Equals MCLK 44 MCLK Divide By 2 44 MCLK Disable 44

Clocking Control 2 Address 05h 44 Speed Mode 44 32 kHz Sample Rate Group 45 Internal MCLK/LRCK Ratio 45

Class H Power Control Address 06h 45 Adaptive Power Adjustment 45

Miscellaneous Control Address 07h 45 Digital MUX 45 Analog Zero Cross 46 Digital Soft Ramp 46 Freeze Registers 46

ADC, Line, HP MUX Address 08h 46 ADC x Input Select 46 Line Input Select 47 Headphone Input Select 47

HPF Control Address 09h 47 ADCx High-Pass Filter 47 ADCx High-Pass Filter Freeze 47 HPF x Corner Frequency 47

Misc. ADC Control Address 0Ah 48 ADC Channel B=A 48 PGA Channel B=A 48 Digital Sum 48 Invert ADC Signal Polarity 48 ADC Mute 48

PGA x MUX, Volume PGA A Address 0Bh & PGA B Address 0Ch 49

Boostx 49 PGA x Input Select 49 PGAx Volume 49 ADCx Attenuator Control ADCAATT Address 0Dh & ADCBATT Address 0Eh 50 ADCx Volume 50 Playback Control 1 Address 0Fh 50 Power Down DSP 50 HP/Line De-Emphasis 50 Playback Channels B=A 50

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Invert PCM Signal Polarity 51 Master Playback Mute 51 ADCx Mixer Volume ADCA Address 10h & ADCB Address 11h 51 ADC Mixer Channel x Mute 51 ADC Mixer Channel x Volume 51 PCMx Mixer Volume PCMA Address 12h & PCMB Address 13h 52 PCM Mixer Channel x Mute 52 PCM Mixer Channel x Volume 52 Beep Frequency & On Time Address 14h 53 Beep Frequency 53 Beep On Time 54 Beep Volume & Off Time Address 15h 54 Beep Off Time 54 Beep Volume 55 Beep & Tone Configuration Address 16h 55 Beep Configuration 55 Treble Corner Frequency 55 Bass Corner Frequency 56 Tone Control Enable 56 Tone Control Address 17h 56 Treble Gain 56 Bass Gain 56 Master Volume Control MSTA Address 18h & MSTB Address 19h 57 Master Volume Control 57 Headphone Volume Control HPA Address 1Ah & HPB Address 1Bh 57 Headphone Channel x Mute 57 Headphone Volume Control 57 Line Volume Control LINEA Address 1Ch & LINEB Address 1Dh 58 Line Channel x Mute 58 Line Volume Control 58 Analog Input Advisory Volume Address 1Eh 59 Analog Input Advisory Volume 59 Digital Input Advisory Volume Address 1Fh 59 Digital Input Advisory Volume 59 ADC & PCM Channel Mixer Address 20h 60 PCM Mix Channel Swap 60 ADC Mix Channel Swap 60 Limiter Min/Max Thresholds Address 21h 60 Limiter Maximum Threshold 60 Limiter Cushion Threshold 61 Limiter Control, Release Rate Address 22h 61 Peak Detect and Limiter 61 Peak Signal Limit All Channels 61 Limiter Release Rate 62 Limiter Attack Rate Address 23h 62 Limiter Attack Rate 62 ALC Enable & Attack Rate Address 24h 62 ALCx 62 ALC Attack Rate 63

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ALC Release Rate Address 25h 63 ALC Release Rate 63

ALC Threshold Address 26h 64 ALC Maximum Threshold 64 ALC Minimum Threshold 64

Noise Gate Control Address 27h 64 Noise Gate All Channels 64 Noise Gate Enable 65 Noise Gate Threshold and Boost 65 Noise Gate Delay Timing 65

ALC and Limiter Soft Ramp, Zero Cross Disables Address 28h 65 ALCx Soft Ramp Disable 65 ALCx Zero Cross Disable 65 Limiter Soft Ramp Disable 66

Status Address 29h Read Only 66 HPDETECT Pin Status Read Only 66 Serial Port Clock Error Read Only 66 DSP Engine Overflow Read Only 66 MIXx Overflow Read Only 66 ADCx Overflow Read Only 67

Charge Pump Frequency Address 2Ah 67 Charge Pump Frequency 67

PCB LAYOUT CONSIDERATIONS 68 Power Supply 68 Grounding 68 QFN Thermal Pad 68

ANALOG VOLUME NON-LINEARITY DNL & INL 69 ADC & DAC DIGITAL FILTERS 70 PARAMETER DEFINITIONS 71 PACKAGE DIMENSIONS 72
LIST OF FIGURES

Figure 1.Typical Connection Diagram 10 Figure 2.CMRR Test Configuration 12 Figure 3.HP Output Test Configuration 15 Figure 4.Line Output Test Configuration 15 Figure 5.Serial Port Timing Slave Mode 17 Figure 6.Serial Port Timing Master Mode 17 Figure Control Port Timing 18 Figure 8.Power Consumption Test Configuration 19 Figure 9.Analog Input Signal Flow 23 Figure 10.Stereo Pseudo-Differential Input 24 Figure 11.ALC Operation 25 Figure 12.DSP Engine Signal Flow 26 Figure 13.Analog Output Stage 27 Figure 14.Adaptive Mode 00 28 Figure 15.VHPFILT Transitions 30 Figure 16.VHPFILT Hysteresis 30 Figure 17.Class H Power to Load vs. Power from VCP Supply 31

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Figure 18.Beep Configuration Options 32 Figure 19.Peak Detect & Limiter 33 Figure Format 34 Figure 21.Control Port Timing, Write 38 Figure 22.Control Port Timing, Read 38 Figure 23.PGA Step Size vs. Volume Setting 69 Figure 24.PGA Output Volume vs. Volume Setting 69 Figure 25.HP/Line Step Size vs. Volume Setting 69 Figure 26.HP/Line Output Volume vs. Volume Setting 69 Figure 27.ADC Passband Ripple 70 Figure 28.ADC Stopband Rejection 70 Figure 29.ADC Transition Band 70 Figure 30.ADC Transition Band Detail 70 Figure 31.DAC Passband Ripple 70 Figure 32.DAC Stopband 70 Figure 33.DAC Transition Band 70 Figure 34.DAC Transition Band Detail 70

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PIN DESCRIPTIONS

CS42L55

SCLK MCLK SDOUT VL VDFILT VLDO RESET HPDETECT AIN1B

SDIN 1

LRCK 2 SDA 3 SCL 4 VCP 5 FLYP 6
+VHPFILT 7 FLYC 8 FLYN 9
36 35 34 33 32 31 30 29 28

GND/Thermal Pad

Top-Down Through Package View
27 AIN1REF 26 AIN1A 25 AIN2B 24 AIN2REF 23 AIN2A 22 AFILTB 21 AFILTA 20 VQ 19 FILT+
10 11 12 13 14 15 16 17 18
-VHPFILT HPOUTA

HPREF HPOUTB LINEOUTA LINEREF LINEOUTB

VA AGND

Pin Name SDIN LRCK SDA SCL VCP FLYP
+VHPFILT

FLYC

FLYN
-VHPFILT HPOUTA HPOUTB HPREF LINEOUTA LINEOUTB LINEREF

Pin Description
1 Serial Audio Data Input - Input for two’s complement serial audio data.

Left Right Clock Input/Output - Determines which channel, Left or Right, is currently active on the serial audio data lines.
3 Serial Control Data Input/Output - Serial data for the serial control port.
4 Serial Control Port Clock Input - Serial clock for the serial control port.
5 Step-Down Charge Pump Power Input - Power supply for the step-down charge pump.

Charge Pump Cap Positive Node Output - Positive node for the step-down charge pump’s flying capacitor.

Step-Down Charge Pump Filter Connection Output - Power supply from the step-down charge pump that provides the positive rail for the headphone and line amplifiers

Charge Pump Cap Common Node Output - Common positive node for the step-down and inverting charge pumps’ flying capacitors.

Charge Pump Cap Negative Node Output - Negative node for the inverting charge pump’s flying capacitor.

Inverting Charge Pump Filter Connection Output - Power supply from the inverting charge pump that provides the negative rail for the headphone and line amplifiers.
11 Headphone Audio Output - The full-scale output level is specified in the HP Output Charac13 teristics specification table
12 Pseudo Diff. Headphone Output Reference Input - Ground reference for the headphone amplifiers
14 Line Audio Output - The full-scale output level is specified in the Line Output Characteristics 16 specification table
15 Pseudo Diff. Line Output Reference Input - Ground reference for the line amplifiers.

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12.ORDERING INFORMATION

Product Description Ultra Low Power, Stereo

CS42L55 CODEC w/ Class H HP Amp for Portable Apps

CDB42L55 CS42L55 Evaluation Board

Package 36L-QFN

Pb-Free YES

Grade Temp Range Container Order #

Rail

CS42L55-CNZ

Commercial -40°C to +85°C Tape & Reel CS42L55-CNZR

CDB42L55
13.REFERENCES

Philips Semiconductor, The Specification Version January
14.REVISION HISTORY

Initial Release

Changes

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE “CRITICAL APPLICATIONS” . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
is a registered trademark of Philips Semiconductor.

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Datasheet ID: CS42L55-CNZ 523172