74F899SC

74F899SC Datasheet

74F899 9-Bit Latchable Transceiver

Part	Datasheet
74F899SC	74F899SC (pdf)

Related Parts	Information
74F899QC	74F899QC
74F899SCX	74F899SCX
74F899QCX	74F899QCX

PDF Datasheet Preview
74F899 9-Bit Latchable Transceiver 74F899 9-Bit Latchable Transceiver with Parity Generator/Checker The 74F899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. It has a guaranteed current sinking capability of 24 mA at the A-bus and 64 mA at the B-bus. The 74F899 features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. s Latchable transceiver with output sink of 24 mA at the A-bus and 64 mA at the B-bus s Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A s Independent latch enables for A-to-B and B-to-A directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking s Ability to simultaneously generate and check parity s May be used in systems applications in place of the 74F543 and 74F280 s May be used in system applications in place of the 74F657 and 74F373 no need to change T/R to check parity Ordering Code: Order Number Package Number Package Description 74F899SC M28B 28-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F899QC V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for SOIC Pin Assignment for PCC Logic Symbol 1999 Fairchild Semiconductor Corporation DS010195 74F899 Input Loading/Fan-Out Pin Names APAR BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB Data Inputs/ Data Outputs Data Inputs/ Data Outputs A Bus Parity Input/Output B Bus Parity Input/Output Parity Select Input Output Enable Inputs Mode Select Input Latch Enable Inputs Error Signal Outputs HIGH/LOW U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/−0.6 mA 150/40 −3 mA/24 mA 20 µA/−0.6 mA −12 mA/64 mA 20 µA/−0.6 mA 150/40 −3 mA/24 mA 20 µA/−0.6 mA −12 mA/64 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Pin Descriptions Pin Names APAR, BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB Description A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs ODD/EVEN Parity Select, Active LOW for EVEN Parity Output Enables for A or B Bus, Active LOW Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode Latch Enables for A and B Latches, HIGH for Transparent Mode Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs Functional Description The 74F899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. • Bus A B communicates to Bus B A , parity is generated and passed on to the B A Bus as BPAR APAR . If LEB LEA is HIGH and the Mode Select SEL is LOW, the parity generated from B[0:7] A[0:7] can be checked and monitored by ERRB ERRA . • Bus A B communicates to Bus B A in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode can be used as an interrupt to signal a data/parity bit error to the CPU . • Independent Latch Enables LEA and LEB allow other permutations of generating/checking see Function Table .

PDF Datasheet Preview

74F899 9-Bit Latchable Transceiver
74F899 9-Bit Latchable Transceiver with Parity Generator/Checker

The 74F899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. It has a guaranteed current sinking capability of 24 mA at the A-bus and 64 mA at the B-bus.

The 74F899 features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
s Latchable transceiver with output sink of 24 mA at the A-bus and 64 mA at the B-bus
s Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A
s Independent latch enables for A-to-B and B-to-A directions
s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking s Ability to simultaneously generate and check parity s May be used in systems applications in place of the
74F543 and 74F280 s May be used in system applications in place of the
74F657 and 74F373 no need to change T/R to check parity
Ordering Code:

Order Number Package Number

Package Description
74F899SC

M28B
28-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F899QC

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignment for SOIC

Pin Assignment for PCC

Logic Symbol
1999 Fairchild Semiconductor Corporation DS010195
74F899

Input Loading/Fan-Out

Pin Names

APAR

BPAR

ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB

Data Inputs/ Data Outputs Data Inputs/ Data Outputs A Bus Parity Input/Output B Bus Parity Input/Output Parity Select Input Output Enable Inputs Mode Select Input Latch Enable Inputs Error Signal Outputs

HIGH/LOW

U.L.

Input IIH/IIL

HIGH/LOW

Output IOH/IOL
20 µA/−0.6 mA
150/40
−3 mA/24 mA
20 µA/−0.6 mA
−12 mA/64 mA
20 µA/−0.6 mA
150/40
−3 mA/24 mA
20 µA/−0.6 mA
−12 mA/64 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA

Pin Descriptions

Pin Names APAR, BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB

Description A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs ODD/EVEN Parity Select, Active LOW for EVEN Parity Output Enables for A or B Bus, Active LOW Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode Latch Enables for A and B Latches, HIGH for Transparent Mode Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs

Functional Description

The 74F899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions.
• Bus A B communicates to Bus B A , parity is generated and passed on to the B A Bus as BPAR APAR . If LEB LEA is HIGH and the Mode Select SEL is LOW, the parity generated from B[0:7] A[0:7] can be checked and monitored by ERRB ERRA .
• Bus A B communicates to Bus B A in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode can be used as an interrupt to signal a data/parity bit error to the CPU .
• Independent Latch Enables LEA and LEB allow other permutations of generating/checking see Function Table .

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Datasheet ID: 74F899SC 513380