74F841SPC

74F841SPC Datasheet

74F841 10-Bit Transparent Latch

Part	Datasheet
74F841SPC	74F841SPC (pdf)

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74F841 10-Bit Transparent Latch 74F841 10-Bit Transparent Latch The 74F841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 74F841 is a 10-bit transparent latch, a 10-bit version of the 74F373. s 3-STATE output Ordering Code: Order Number Package Number Package Description 74F841SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F841SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009599 74F841 Unit Loading/Fan Out Pin Names Data Inputs 3-STATE Outputs Output Enable Input Latch Enable Functional Description The 74F841 device consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state. Logic Diagram U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −3 mA/24 mA 20 µA/−0.6 mA 20 µA/−0.6 mA Function Table Inputs OE LE D XXX HH L HHH HLX LHL L HH LLX LXX HLX H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance NC = No Change Internal Q X L H NC L H NC H L H L H Output O Function Z High Z Z High Z Z High Z Z Latched L Transparent H Transparent NC Latched H Preset L Clear H Preset Z Latched Z Latched Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F841 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C

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74F841 10-Bit Transparent Latch
74F841 10-Bit Transparent Latch

The 74F841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 74F841 is a 10-bit transparent latch, a 10-bit version of the 74F373.
s 3-STATE output
Ordering Code:

Order Number Package Number

Package Description
74F841SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F841SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009599
74F841

Unit Loading/Fan Out

Pin Names

Data Inputs 3-STATE Outputs Output Enable Input Latch Enable

Functional Description

The 74F841 device consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition.

On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state.

Logic Diagram

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −3 mA/24 mA 20 µA/−0.6 mA 20 µA/−0.6 mA

Function Table

Inputs

OE LE D XXX HH L HHH HLX LHL L HH LLX LXX HLX

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance NC = No Change

Internal

Q X L H NC L H NC H L H L H

Output O

Function

Z High Z

Z High Z

Z High Z

Z Latched

L Transparent

H Transparent

NC Latched

H Preset

L Clear

H Preset

Z Latched

Z Latched

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F841

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

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Datasheet ID: 74F841SPC 513377