74F676SC

74F676SC Datasheet

74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register

Part	Datasheet
74F676SC	74F676SC (pdf)

Related Parts	Information
74F676SCX	74F676SCX
74F676PC	74F676PC
74F676SPC	74F676SPC

PDF Datasheet Preview
74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode M input is HIGH, information present on the parallel data inputs is entered on the falling edge of the Clock Pulse CP input signal. When M is LOW, data is shifted out of the most significant bit position while information present on the Serial SI input shifts into the least significant bit position. A HIGH signal on the Chip Select CS input prevents both parallel and serial operations. s 16-bit parallel-to-serial conversion s 16-bit serial-in, serial-out s Chip select control s Slim 24 lead 300 mil package Ordering Code: Order Number Package Number Package Description 74F676SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F676PC N24A 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-011, Wide 74F676SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2002 Fairchild Semiconductor Corporation DS009588 74F676 Unit Loading/Fan Out Pin Names CS CP M SI SO Parallel Data Inputs Chip Select Input Active LOW Clock Pulse Input Active LOW Mode Select Input Serial Data Input Serial Output U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table. a HIGH signal on the Chip Select CS input prevents clocking, and data is stored in the sixteen registers. Shift/Serial data present on the SI pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks, finally appearing on the SO pin. Parallel data present on are entered into the register on the falling edge of CP. The SO output represents the Q15 register output. To prevent false clocking, CP must be LOW during a LOW-to-HIGH transition of CS. Block Diagram Shift Register Operations Table Control Input H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = HIGH-to-LOW Transition Operating Mode Hold Shift/Serial Load Parallel Load 74F676 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage

PDF Datasheet Preview

74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register
74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register

The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode M input is HIGH, information present on the parallel data inputs is entered on the falling edge of the Clock Pulse CP input signal. When M is LOW, data is shifted out of the most significant bit position while information present on the Serial SI input shifts into the least significant bit position. A HIGH signal on the Chip Select CS input prevents both parallel and serial operations.
s 16-bit parallel-to-serial conversion s 16-bit serial-in, serial-out s Chip select control s Slim 24 lead 300 mil package
Ordering Code:

Order Number Package Number

Package Description
74F676SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F676PC

N24A
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-011, Wide
74F676SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2002 Fairchild Semiconductor Corporation DS009588
74F676

Unit Loading/Fan Out

Pin Names

CS CP M SI SO

Parallel Data Inputs Chip Select Input Active LOW Clock Pulse Input Active LOW Mode Select Input Serial Data Input Serial Output

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA

Functional Description

The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table. a HIGH signal on the Chip Select CS input prevents clocking, and data is stored in the sixteen registers. Shift/Serial data present on the SI pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks, finally appearing on the SO pin. Parallel data present on are entered into the register on the falling edge of CP. The SO output represents the Q15 register output. To prevent false clocking, CP must be LOW during a LOW-to-HIGH transition of CS.

Block Diagram

Shift Register Operations Table

Control Input

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = HIGH-to-LOW Transition

Operating Mode

Hold Shift/Serial Load Parallel Load
74F676

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage

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Datasheet ID: 74F676SC 513368