74F657SPC

74F657SPC Datasheet

74F657 Octal Bidirectional Transceiver with

Part	Datasheet
74F657SPC	74F657SPC (pdf)

Related Parts	Information
74F657SC	74F657SC

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74F657 Octal Bidirectional Transceiver with 74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs The 74F657 contains eight non-inverting buffers with 3STATE outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA at the A Port and 64 mA at the B Port. s 300 Mil 24-pin slimline DIP s Combines 74F245 and 74F280A functions in one package s 3-STATE outputs s B Outputs sink 64 mA s 12 mA source current, B side s Input diodes for termination effects Ordering Code: Order Number Package Number Package Description 75F657SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F657SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-100, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 1999 Fairchild Semiconductor Corporation DS009584 74F657 Unit Loading/Fan Out Pin Names T/R OE PARITY ODD/EVEN ERROR Data Inputs/ 3-STATE Outputs Data Inputs/ 3-STATE Outputs Transmit/Receive Input Enable Input Parity Input/ 3-STATE Output ODD/EVEN Parity Input Error Output Functional Description The Transmit/Receive T/R input determines the direction of the data flow through the bidirectional transceivers. Transmit active HIGH enables data from the A Port to the B Port Receive active LOW enables data from the B Port to the A Port. The Output Enable OE input disables the parity and ERROR outputs and both the A and B Ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH. When transmitting T/R HIGH , the parity generator detects whether an even or odd number of bits on the A Port are HIGH and compares these with the condition of the parity U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 90 µA/− 90 µA −3 mA/24 mA 20 mA 70 µA/−70 µA −12 mA/64 mA 48 mA 40 µA/−40 µA 40 µA/−40 µA 70 µA/−70µA −12 mA/64 mA 48 mA 20 µA/−20 µA −12 mA/64 mA 48 mA select ODD/EVEN . If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH. In receiving mode T/R LOW , the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error. Function Table Function Table Input/ Number of Inputs Output Outputs Inputs that are HIGH ODD/ Outputs OE T/R Parity ERROR EVEN Mode 0, 2, 4, 6, 8 L H Z Transmit Z Transmit H Receive L Receive L Receive

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74F657 Octal Bidirectional Transceiver with
74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs

The 74F657 contains eight non-inverting buffers with 3STATE outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA at the A Port and 64 mA at the B Port.
s 300 Mil 24-pin slimline DIP s Combines 74F245 and 74F280A functions in one
package s 3-STATE outputs s B Outputs sink 64 mA s 12 mA source current, B side s Input diodes for termination effects
Ordering Code:

Order Number Package Number

Package Description
75F657SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F657SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-100, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
1999 Fairchild Semiconductor Corporation DS009584
74F657

Unit Loading/Fan Out

Pin Names

T/R OE PARITY

ODD/EVEN ERROR

Data Inputs/ 3-STATE Outputs Data Inputs/ 3-STATE Outputs Transmit/Receive Input Enable Input Parity Input/ 3-STATE Output ODD/EVEN Parity Input Error Output

Functional Description

The Transmit/Receive T/R input determines the direction of the data flow through the bidirectional transceivers. Transmit active HIGH enables data from the A Port to the B Port Receive active LOW enables data from the B Port to the A Port.

The Output Enable OE input disables the parity and ERROR outputs and both the A and B Ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH.

When transmitting T/R HIGH , the parity generator detects whether an even or odd number of bits on the A Port are HIGH and compares these with the condition of the parity

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 90 µA/− 90 µA −3 mA/24 mA 20 mA 70 µA/−70 µA −12 mA/64 mA 48 mA 40 µA/−40 µA 40 µA/−40 µA 70 µA/−70µA −12 mA/64 mA 48 mA 20 µA/−20 µA −12 mA/64 mA 48 mA
select ODD/EVEN . If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH.

In receiving mode T/R LOW , the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error.

Function Table

Function Table

Input/

Number of

Inputs

Output

Outputs

Inputs that
are HIGH

ODD/

Outputs

OE T/R

Parity ERROR

EVEN

Mode
0, 2, 4, 6, 8 L H

Z Transmit

Z Transmit

H Receive

L Receive

L Receive

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Datasheet ID: 74F657SPC 513365