74F573SJX

74F573SJX Datasheet

74F573 Octal D-Type Latch with 3-STATE Outputs

Part	Datasheet
74F573SJX	74F573SJX (pdf)

Related Parts	Information
74F573SCX	74F573SCX
74F573SJ	74F573SJ
74F573PC	74F573PC
74F573SC	74F573SC

PDF Datasheet Preview
74F573 Octal D-Type Latch with 3-STATE Outputs 74F573 Octal D-Type Latch with 3-STATE Outputs The 74F573 is a high speed octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs. This device is functionally identical to the 74F373 but has different pinouts. s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74F373 s 3-STATE outputs for bus interfacing s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number Package Number Package Description 74F573SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F573SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F573PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009566 74F573 Unit Loading/Fan Out Pin Names LE OE Data Inputs Latch Enable Input Active HIGH 3-STATE Output Enable Input Active LOW 3-STATE Latch Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Functional Description The 74F573 contains eight D-type latches with 3-state output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Function Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle Outputs O H L O0 Z Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F573 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA ESD Last Passing Voltage Min 4000V

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74F573 Octal D-Type Latch with 3-STATE Outputs
74F573 Octal D-Type Latch with 3-STATE Outputs

The 74F573 is a high speed octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs.

This device is functionally identical to the 74F373 but has different pinouts.
s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
s Useful as input or output port for microprocessors s Functionally identical to 74F373 s 3-STATE outputs for bus interfacing s Guaranteed 4000V minimum ESD protection
Ordering Code:

Order Number Package Number

Package Description
74F573SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F573SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F573PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009566
74F573

Unit Loading/Fan Out

Pin Names

LE OE

Data Inputs Latch Enable Input Active HIGH 3-STATE Output Enable Input Active LOW 3-STATE Latch Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA

Functional Description

The 74F573 contains eight D-type latches with 3-state output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Function Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle

Outputs

O H L O0 Z

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F573

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

ESD Last Passing Voltage Min
4000V

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Datasheet ID: 74F573SJX 513354