74ABT574CMTCX

74ABT574CMTCX Datasheet

74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74ABT574CMTCX	74ABT574CMTCX (pdf)

Related Parts	Information
74ABT574CMTC	74ABT574CMTC
74ABT574CSJ	74ABT574CSJ
74ABT574CSC	74ABT574CSC
74ABT574CMSAX	74ABT574CMSAX
74ABT574CMSA	74ABT574CMSA
74ABT574CSJX	74ABT574CSJX
74ABT574CSCX	74ABT574CSCX

PDF Datasheet Preview
74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs 74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs The ABT574 is an octal flip-flop with a buffered common Clock CP and a buffered common Output Enable OE . The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock CP transition. The device is functionally identical to the ABT374 but has broadside pinouts. s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to ABT374 s 3-STATE outputs for bus-oriented applications s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching, noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability Ordering Code: Order Number Package Number Package Description 74ABT574CSC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ABT574CSJ M20D Pb-Free 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ABT574CMSA MSA20 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide 74ABT574CMTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names Data Inputs Clock Pulse Input Active Rising Edge 3-STATE Output Enable Input Active LOW 3-STATE Outputs 2005 Fairchild Semiconductor Corporation DS011511 74ABT574 Functional Description The ABT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock CP transition. Function Table With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops. OE H L H HIGH Voltage Level L LOW Voltage Level X Immaterial High Impedance LOW-to-HIGH Transition NC No Change Logic Diagram Inputs CP H or L H or L H or L H or L Internal Outputs Function Hold Hold Load Load Data Available Data Available NC No Change in Data NC No Change in Data Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ABT574 Absolute Maximum Ratings Note 1 Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 mA to mA Voltage Applied to Any Output in the Disabled or

PDF Datasheet Preview

74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs
74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs

The ABT574 is an octal flip-flop with a buffered common Clock CP and a buffered common Output Enable OE . The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock CP transition.

The device is functionally identical to the ABT374 but has broadside pinouts.
s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
s Useful as input or output port for microprocessors s Functionally identical to ABT374 s 3-STATE outputs for bus-oriented applications s Output sink capability of 64 mA, source capability
of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and
250 pF loads s Guaranteed simultaneous switching, noise level and
dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:

Order Number Package Number

Package Description
74ABT574CSC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ABT574CSJ

M20D

Pb-Free 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ABT574CMSA

MSA20
20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide
74ABT574CMTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Descriptions

Pin Names

Data Inputs Clock Pulse Input Active Rising Edge
3-STATE Output Enable Input Active LOW
3-STATE Outputs
2005 Fairchild Semiconductor Corporation DS011511
74ABT574

Functional Description

The ABT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock CP transition.

Function Table

With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops.

OE H L

H HIGH Voltage Level L LOW Voltage Level X Immaterial

High Impedance LOW-to-HIGH Transition NC No Change

Logic Diagram

Inputs

CP H or L H or L

H or L H or L

Internal Outputs

Function

Hold

Hold

Load

Load

Data Available

Data Available

NC No Change in Data

NC No Change in Data

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ABT574

Absolute Maximum Ratings Note 1

Storage Temperature

Ambient Temperature under Bias

Junction Temperature under Bias

VCC Pin Potential to Ground Pin Input Voltage Note 2

Input Current Note 2
mA to mA

Voltage Applied to Any Output
in the Disabled or

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Datasheet ID: 74ABT574CMTCX 513063