74F552QC

74F552QC Datasheet

74F552 Octal Registered Transceiver with Parity and Flags

Part	Datasheet
74F552QC	74F552QC (pdf)

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74F552 Octal Registered Transceiver with Parity and Flags 74F552 Octal Registered Transceiver with Parity and Flags The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the output enable returns to HIGH after reading the output port. Each register has a separate output enable control for its 3-STATE buffer. The separate Clocks, Flags, and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A Port to the B Port, a parity bit is generated. On the other hand, when data is transferred from the B Port to the A Port, the parity of input data on is checked. s 8-Bit bidirectional I/O Port with handshake s Register status flag flip-flops s Separate clock enable and output enable s Parity generation and parity check s B-outputs sink 64 mA s 3-STATE outputs Ordering Code: Order Number Package Number Package Description 74F552SC M28B 28-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F552QC V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for SOIC Pin Assignments for PLCC 2000 Fairchild Semiconductor Corporation DS009561 74F552 Logic Symbols IEEE/IEC Unit Loading/Fan Out Pin Names FR FS PARITY ERROR CER CES CPR CPS OEBR OEAS Description A-to-B Port Data Inputs or U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 70 µA/−0.65 mA B-to-A 3-STATE 150/40 −3 mA/24 mA 20 mA B-to-A Transceiver Inputs or 70 µA/−0.65 mA A-to-B 3-STATE Output B Port Flag Output 80 −12 mA/64 mA 48 mA −1 mA/20 mA A Port Flag Output −1 mA/20 mA Parity Bit Transceiver Input or Output 70 µA/−0.65 mA 50 −12 mA/64 mA 48 mA Parity Check Output Active LOW −1 mA/20 mA R Registers Clock Enable Input Active LOW 20 µA/−0.6 mA S Registers Clock Enable Input Active LOW 20 µA/−0.6 mA R Registers Clock Pulse Input Active Rising Edge 20 µA/−0.6 mA S Registers Clock Pulse Input Active Rising Edge 20 µA/−0.6 mA B Port and PARITY Output Enable Active LOW 20 µA/−1.2 mA and Clear FR Input Active Rising Edge

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74F552 Octal Registered Transceiver with Parity and Flags
74F552 Octal Registered Transceiver with Parity and Flags

The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the output enable returns to HIGH after reading the output port. Each register has a separate output enable control for its 3-STATE buffer. The separate Clocks, Flags, and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A Port to the B Port, a parity bit is generated. On the other hand, when data is transferred from the B Port to the A Port, the parity of input data on is checked.
s 8-Bit bidirectional I/O Port with handshake s Register status flag flip-flops s Separate clock enable and output enable s Parity generation and parity check s B-outputs sink 64 mA s 3-STATE outputs
Ordering Code:

Order Number Package Number

Package Description
74F552SC

M28B
28-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F552QC

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignments for SOIC

Pin Assignments for PLCC
2000 Fairchild Semiconductor Corporation DS009561
74F552

Logic Symbols

IEEE/IEC

Unit Loading/Fan Out

Pin Names

FR FS PARITY

ERROR CER CES CPR CPS OEBR

OEAS

Description A-to-B Port Data Inputs or

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 70 µA/−0.65 mA

B-to-A 3-STATE
150/40 −3 mA/24 mA 20 mA

B-to-A Transceiver Inputs or
70 µA/−0.65 mA

A-to-B 3-STATE Output B Port Flag Output
80 −12 mA/64 mA 48 mA
−1 mA/20 mA

A Port Flag Output
−1 mA/20 mA

Parity Bit Transceiver Input or Output
70 µA/−0.65 mA
50 −12 mA/64 mA 48 mA

Parity Check Output Active LOW
−1 mA/20 mA

R Registers Clock Enable Input Active LOW
20 µA/−0.6 mA

S Registers Clock Enable Input Active LOW
20 µA/−0.6 mA

R Registers Clock Pulse Input Active Rising Edge
20 µA/−0.6 mA

S Registers Clock Pulse Input Active Rising Edge
20 µA/−0.6 mA

B Port and PARITY Output Enable Active LOW
20 µA/−1.2 mA
and Clear FR Input Active Rising Edge

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Datasheet ID: 74F552QC 513350