74F524SC

74F524SC Datasheet

74F524 8-Bit Registered Comparator

Part	Datasheet
74F524SC	74F524SC (pdf)

Related Parts	Information
74F524PC	74F524PC

PDF Datasheet Preview
74F524 8-Bit Registered Comparator 74F524 8-Bit Registered Comparator The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines S0, S1 to execute shift, load, hold and read out. An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing “register equal to bus”, “register greater than bus” and “register less than bus” are provided. These outputs can be disabled to the OFF state by the use of Status Enable SE . A mode control has also been provided to allow twos complement as well as magnitude compare. Linking inputs are provided for expansion to longer words. s 8-Bit bidirectional register with bus-oriented input-output s Independent serial input-output to register s Register bus comparator with “equal to”, “greater than” and “less than” outputs s Cascadable in groups of eight bits s Open-collector comparator outputs for AND-wired expansion s Twos complement or magnitude compare Ordering Code: Order Number Package Number Package Description 74F524SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F524PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 1999 Fairchild Semiconductor Corporation DS009546 74F524 Unit Loading/Fan Out Pin Names U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL S0, S1 C/SI Mode Select Inputs Status Priority or Serial Data Input 20 µA/−0.6 mA 20 µA/−0.6 mA Clock Pulse Input Active Rising Edge 20 µA/−0.6 mA Status Enable Input Active LOW 20 µA/−0.6 mA Compare Mode Select Input 20 µA/−0.6 mA Parallel Data Inputs or 3-STATE Parallel Data Outputs 150/40 70 µA/−0.65 mA −3 mA/24 mA 20 mA C/SO Status Priority or Serial Data Output −1 mA/20 mA Register Less Than Bus Output OC Note 1 Note 1 /20 mA Register Equal Bus Output OC Note 1 Note 1 /20 mA Note 1 OC = Open Collector Register Greater Than Bus Output OC Note 1 Note 1 /20 mA Number Representation Select Table Operation Magnitude Compare Twos Complement Compare Select Truth Table Operation L Data in Shift Register H Contents in Register onto Data Bus, Data Remains in Register Unaffected by Clock

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74F524 8-Bit Registered Comparator
74F524 8-Bit Registered Comparator

The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines S0, S1 to execute shift, load, hold and read out.

An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing “register equal to bus”, “register greater than bus” and “register less than bus” are provided. These outputs can be disabled to the OFF state by the use of Status Enable SE . A mode control has also been provided to allow twos complement as well as magnitude compare. Linking inputs are provided for expansion to longer words.
s 8-Bit bidirectional register with bus-oriented input-output s Independent serial input-output to register s Register bus comparator with “equal to”, “greater than”
and “less than” outputs s Cascadable in groups of eight bits s Open-collector comparator outputs for AND-wired
expansion s Twos complement or magnitude compare
Ordering Code:

Order Number Package Number

Package Description
74F524SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F524PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
1999 Fairchild Semiconductor Corporation DS009546
74F524

Unit Loading/Fan Out

Pin Names

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL

S0, S1 C/SI

Mode Select Inputs Status Priority or Serial Data Input
20 µA/−0.6 mA 20 µA/−0.6 mA

Clock Pulse Input Active Rising Edge
20 µA/−0.6 mA

Status Enable Input Active LOW
20 µA/−0.6 mA

Compare Mode Select Input
20 µA/−0.6 mA

Parallel Data Inputs or 3-STATE Parallel Data Outputs
150/40
70 µA/−0.65 mA −3 mA/24 mA 20 mA

C/SO

Status Priority or Serial Data Output
−1 mA/20 mA

Register Less Than Bus Output

OC Note 1 Note 1 /20 mA

Register Equal Bus Output

OC Note 1 Note 1 /20 mA

Note 1 OC = Open Collector

Register Greater Than Bus Output

OC Note 1 Note 1 /20 mA

Number Representation Select Table

Operation

Magnitude Compare

Twos Complement Compare

Select Truth Table

Operation

L Data in Shift Register

H Contents in Register onto Data Bus,

Data Remains in Register Unaffected by Clock

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Datasheet ID: 74F524SC 513340