74F433SPC

74F433SPC Datasheet

74F433 First-In First-Out FIFO Buffer Memory

Part	Datasheet
74F433SPC	74F433SPC (pdf)

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74F433 First-In First-Out FIFO Buffer Memory 74F433 First-In First-Out FIFO Buffer Memory The 74F433 is an expandable fall-through type high-speed First-In First-Out FIFO Buffer Memory that is optimized for high-speed disk or tape controller and communication buffer applications. It is organized as 64-words by 4-bits and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories. The 74F433 has 3-STATE outputs that provide added versatility, and is fully compatible with all TTL families. s Serial or parallel input s Serial or parallel output s Expandable without additional logic s 3-STATE outputs s Fully compatible with all TTL families s Slim 24-pin package s 9423 replacement Ordering Code: Order Number Package Number Package Description 74F433SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-100, Wide Logic Symbol Connection Diagram 1999 Fairchild Semiconductor Corporation DS009544 74F433 Unit Loading/Fan Out Pin Names PL CPSI IES TTS MR OES TOP TOS CPSO OE DS QS IRF ORE Block Diagram Parallel Load Input Serial Input Clock Serial Input Enable Transfer to Stack Input Master Reset Serial Output Enable Transfer Out Parallel Transfer Out Serial Output Clock Output Enable Parallel Data Inputs Serial Data Input Parallel Data Outputs Serial Data Output Input Register Full Output Register Empty U.L. HIGH/LOW 285/10 285/10 20/5 20/5 Input IIH/IIL Output IOH/IOL 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA mA/16 mA µA/16 mA 400 µA/8 mA 400 µA/8 mA 74F433 Functional Description As shown in the block diagram, the 74F433 consists of three sections: An Input Register with parallel and serial data inputs, as well as control inputs and outputs for input handshaking and expansion. A 4-bit-wide, 62-word-deep fall-through stack with selfcontained control logic. An Output Register with parallel and serial data outputs, as well as control inputs and outputs for output handshaking and expansion. These three sections operate asynchronously and are virtually independent of one another. Input Register Data Entry The Input Register can receive data in either bit-serial or 4bit parallel form. It stores this data until it is sent to the fallthrough stack, and also generates the necessary status and control signals. This 5-bit register see Figure 1 is initialized by setting flipflop F3 and resetting the other flip-flops. The Q-output of the last flip-flop FC is brought out as the Input Register Full IRF signal. After initialization, this output is HIGH. Parallel HIGH on the Parallel Load PL input loads the inputs into the flip-flops and sets the FC flip-flop. This forces the IRF output LOW, indicating that the input register is full. During parallel entry, the Serial Input Clock CPSI input must be LOW. Serial on the Serial Data DS input is serially entered into the shift register F3, F2, F1, F0, FC on each HIGH-to-LOW transition of the CPSI input when the Serial Input Enable IES signal is LOW. During serial entry, the PL input should be LOW. After the fourth clock transition, the four data bits are located in flip-flops The FC flip-flop is set, forcing the IRF output LOW and internally inhibiting CPSI pulses from affecting the register. Figure 2 illustrates the final positions in an 74F433 resulting from a 256-bit serial bit train B0 is the first bit, B255 the last . FIGURE Conceptual Input Section 74F433 FIGURE Final Positions in an 74F433 Resulting from a 256-Bit Serial Train Fall-Through outputs of flip-flops feed the stack. A LOW level on the Transfer to Stack TTS input initiates a fall-through action if the top location of the stack is empty, data is loaded into the stack and the input register is re-initialized. Note that this initialization is delayed until PL is LOW . Thus, automatic FIFO action is achieved by connecting the IRF output to the TTS input. An RS-type flip-flop the initialization flip-flop in the control section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack even though IRF and TTS may still be LOW the initialization flip-flop is not cleared until PL goes LOW. Once in the stack, data falls through automatically, pausing only when it is necessary to wait for an empty next location. In the 74F433, the master reset MR input only initializes the stack control section and does not clear the data. Output Register The Output Register see Figure 3 receives 4-bit data words from the bottom stack location, stores them, and outputs data on a 3-STATE, 4-bit parallel data bus or on a 3STATE serial data bus. The output section generates and receives the necessary status and control signals.

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74F433 First-In First-Out FIFO Buffer Memory
74F433 First-In First-Out FIFO Buffer Memory

The 74F433 is an expandable fall-through type high-speed First-In First-Out FIFO Buffer Memory that is optimized for high-speed disk or tape controller and communication buffer applications. It is organized as 64-words by 4-bits and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories.

The 74F433 has 3-STATE outputs that provide added versatility, and is fully compatible with all TTL families.
s Serial or parallel input s Serial or parallel output s Expandable without additional logic s 3-STATE outputs s Fully compatible with all TTL families s Slim 24-pin package s 9423 replacement
Ordering Code:

Order Number Package Number

Package Description
74F433SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-100, Wide

Logic Symbol

Connection Diagram
1999 Fairchild Semiconductor Corporation DS009544
74F433

Unit Loading/Fan Out

Pin Names

PL CPSI IES TTS MR OES TOP TOS CPSO OE DS QS IRF ORE

Block Diagram

Parallel Load Input Serial Input Clock Serial Input Enable Transfer to Stack Input Master Reset Serial Output Enable Transfer Out Parallel Transfer Out Serial Output Clock Output Enable Parallel Data Inputs Serial Data Input Parallel Data Outputs Serial Data Output Input Register Full Output Register Empty

U.L. HIGH/LOW
285/10 285/10
20/5 20/5

Input IIH/IIL Output IOH/IOL 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA 20 µA/400 µA mA/16 mA µA/16 mA 400 µA/8 mA 400 µA/8 mA
74F433

Functional Description

As shown in the block diagram, the 74F433 consists of three sections:

An Input Register with parallel and serial data inputs, as well as control inputs and outputs for input handshaking and expansion.

A 4-bit-wide, 62-word-deep fall-through stack with selfcontained control logic.

An Output Register with parallel and serial data outputs, as well as control inputs and outputs for output handshaking and expansion.

These three sections operate asynchronously and are virtually independent of one another.

Input Register Data Entry

The Input Register can receive data in either bit-serial or 4bit parallel form. It stores this data until it is sent to the fallthrough stack, and also generates the necessary status and control signals.

This 5-bit register see Figure 1 is initialized by setting flipflop F3 and resetting the other flip-flops. The Q-output of
the last flip-flop FC is brought out as the Input Register Full IRF signal. After initialization, this output is HIGH.

Parallel HIGH on the Parallel Load PL input loads the inputs into the flip-flops and sets the FC flip-flop. This forces the IRF output LOW, indicating that the input register is full. During parallel entry, the Serial Input Clock CPSI input must be LOW.

Serial on the Serial Data DS input is serially entered into the shift register F3, F2, F1, F0, FC on each HIGH-to-LOW transition of the CPSI input when the Serial Input Enable IES signal is LOW. During serial entry, the PL input should be LOW.

After the fourth clock transition, the four data bits are located in flip-flops The FC flip-flop is set, forcing the IRF output LOW and internally inhibiting CPSI pulses from affecting the register. Figure 2 illustrates the final positions in an 74F433 resulting from a 256-bit serial bit train B0 is the first bit, B255 the last .

FIGURE Conceptual Input Section
74F433

FIGURE Final Positions in an 74F433 Resulting from a 256-Bit Serial Train

Fall-Through outputs of flip-flops feed the stack. A LOW level on the Transfer to Stack TTS input initiates a fall-through action if the top location of the stack is empty, data is loaded into the stack and the input register is re-initialized. Note that this initialization is delayed until PL is LOW . Thus, automatic FIFO action is achieved by connecting the IRF output to the TTS input.

An RS-type flip-flop the initialization flip-flop in the control section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack even though IRF and TTS may still be LOW the initialization flip-flop is not cleared until PL goes LOW.

Once in the stack, data falls through automatically, pausing only when it is necessary to wait for an empty next location. In the 74F433, the master reset MR input only initializes the stack control section and does not clear the data.

Output Register

The Output Register see Figure 3 receives 4-bit data words from the bottom stack location, stores them, and outputs data on a 3-STATE, 4-bit parallel data bus or on a 3STATE serial data bus. The output section generates and receives the necessary status and control signals.

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Datasheet ID: 74F433SPC 513337