CY62128BNLL-55ZXI

CY62128BNLL-55ZXI Datasheet


CY62128BN

Part Datasheet
CY62128BNLL-55ZXI CY62128BNLL-55ZXI CY62128BNLL-55ZXI (pdf)
Related Parts Information
CY62128BNLL-55SXI CY62128BNLL-55SXI CY62128BNLL-55SXI
CY62128BNLL-70ZAXET CY62128BNLL-70ZAXET CY62128BNLL-70ZAXET
CY62128BNLL-70ZXAT CY62128BNLL-70ZXAT CY62128BNLL-70ZXAT
CY62128BNLL-70ZXA CY62128BNLL-70ZXA CY62128BNLL-70ZXA
CY62128BNLL-70SXA CY62128BNLL-70SXA CY62128BNLL-70SXA
CY62128BNLL-70SXE CY62128BNLL-70SXE CY62128BNLL-70SXE
CY62128BNLL-70ZAXE CY62128BNLL-70ZAXE CY62128BNLL-70ZAXE
CY62128BNLL-70SXAT CY62128BNLL-70SXAT CY62128BNLL-70SXAT
CY62128BNLL-70SXET CY62128BNLL-70SXET CY62128BNLL-70SXET
PDF Datasheet Preview
CY62128BN
1-Mbit 128K x 8 Static RAM
• Temperature Ranges Commercial 0°C to 70°C Industrial to 85°C Automotive-A to 85°C Automotive-E to 125°C
• operation
• CMOS for optimum speed/power
• Low active power
70 ns Commercial, Industrial, Automotive-A mW max. 15 mA
• Low standby power 55/70 ns Commercial, Industrial, Automotive-A 110 µW max. 15 µA
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
• Available in Pb-free and non-Pb-free 32-pin 450 mil-wide SOIC, 32-pin STSOP and 32-pin TSOP-I

Functional Description[1]

The CY62128BN is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable CE2 , an active LOW Output Enable OE , and tri-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected.

Writing to the device is accomplished by taking Chip Enable One CE1 and Write Enable WE inputs LOW and Chip Enable Two CE2 input HIGH. Data on the eight I/O pins I/O0 through I/O7 is then written into the location specified on the address pins A0 through A16 . Reading from the device is accomplished by taking Chip Enable One CE1 and Output Enable OE LOW while forcing Write Enable WE and Chip Enable Two CE2 HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins I/O0 through I/O7 are placed in a high-impedance state when the device is deselected CE1 HIGH or CE2 LOW , the outputs are disabled OE HIGH , or during a write operation CE1 LOW, CE2 HIGH, and WE LOW .

Logic Block Diagram

A0 A1 A2 A3 A4 A5 A6 A7 A8

CCEE12 WE

ROW DECODER SENSE AMPS

INPUT BUFFER
128K x 8 ARRAY

COLUMN DECODER

POWER DOWN

Pin Configuration

Top View SOIC
32 VCC

A16 2
31 A15

A14 3
30 CE2

I/O 0

A12 4
29 WE
28 A13

I/O 1
27 A8
26 A9

I/O 2
25 A11
24 OE

I/O 3

A2 10
23 A10

A1 11
22 CE1

I/O 4

A0 12
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type

CY62128BNLL-55SC
51-85081 32-pin 450-Mil SOIC

CY62128BNLL-55SXC
32-pin 450-Mil SOIC Pb-Free

CY62128BNLL-55SI
32-pin 450-Mil SOIC

CY62128BNLL-55SXI
32-pin 450-Mil SOIC Pb-Free

CY62128BNLL-55ZAI
51-85094 32-pin STSOP

CY62128BNLL-55ZAXI
32-pin STSOP Pb-Free

CY62128BNLL-55ZI
51-85056 32-pin TSOP Type I

CY62128BNLL-55ZXI
32-pin TSOP Type I Pb-Free

CY62128BNLL-70SC
51-85081 32-pin 450-Mil SOIC

CY62128BNLL-70SXC
32-pin 450-Mil SOIC Pb-Free

CY62128BNLL-70ZC
51-85056 32-pin TSOP Type I

CY62128BNLL-70ZXC
32-pin TSOP Type I Pb-Free

CY62128BNLL-70SI
51-85081 32-pin 450-Mil SOIC

CY62128BNLL-70SXI
32-pin 450-Mil SOIC Pb-Free

CY62128BNLL-70ZAI
51-85094 32-pin STSOP

CY62128BNLL-70ZAXI
32-pin STSOP Pb-Free

CY62128BNLL-70ZI
51-85056 32-pin TSOP Type I

CY62128BNLL-70ZXI
32-pin TSOP Type I Pb-Free

CY62128BNLL-70ZXA
51-85056 32-pin TSOP Type I Pb-Free
*A 488954 See ECN NXR Added Automotive product Removed RTSOP Package Updated ordering Information table

CY62128BN

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Datasheet ID: CY62128BNLL-55ZXI 507805