74F283PC

74F283PC Datasheet

74F283 4-Bit Binary Full Adder with Fast Carry

Part	Datasheet
74F283PC	74F283PC (pdf)

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74F283 4-Bit Binary Full Adder with Fast Carry 74F283 4-Bit Binary Full Adder with Fast Carry The 74F283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary words and a Carry input C0 . It generates the binary Sum outputs and the Carry output C4 from the most significant bit. The 74F283 will operate with either active HIGH or active LOW operands positive or negative logic . Ordering Code: Order Number 74F283SC 74F283PC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Logic Symbols Connection Diagram IEEE/IEC Unit Loading/Fan Out Pin Names Description C0 C4 A Operand Inputs B Operand Inputs Carry Input Sum Outputs Carry Output U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/−1.2 mA 20 µA/−1.2 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA 2004 Fairchild Semiconductor Corporation DS009513 74F283 Functional Description The 74F283 adds two 4-bit binary words A plus B plus the incoming Carry C0 . The binary sum appears on the Sum and outgoing carry C4 outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. 20 A0 + B0 + C0 + 21 A1 + B1 + 22 A2 + B2 + 23 A3 + B3 = S0 + 2S1 + 4S2 + 8S3 + 16C4 Where + = plus Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the 74F283 can be used either with all inputs and outputs active HIGH positive logic or with all inputs and outputs active LOW negative logic . See Figure Note that if C0 is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic. Due to pin limitations, the intermediate carries of the 74F283 are not brought out for use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2 shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder A3, B3 LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the 74F283 into a 2-bit and a 1-bit adder. The third stage adder A2, B2, S2 is used merely as a means of getting a carry C10 signal into the fourth stage via A2 and B2 and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I5 that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs are true, the output M5 is true. C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4 Logic Levels L LHLHHL LHHHL LH Active HIGH 00101100111001 Active LOW 11010011000110

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74F283 4-Bit Binary Full Adder with Fast Carry
74F283
4-Bit Binary Full Adder with Fast Carry

The 74F283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary words and a Carry input C0 . It generates the binary Sum outputs and the Carry output C4 from the most significant bit. The 74F283 will operate with either active HIGH or active LOW operands positive or negative logic .
Ordering Code:

Order Number 74F283SC 74F283PC

Package Number

Package Description

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Logic Symbols

Connection Diagram

IEEE/IEC

Unit Loading/Fan Out

Pin Names Description

C0 C4

A Operand Inputs B Operand Inputs Carry Input Sum Outputs Carry Output

U.L.

Input IIH/IIL

HIGH/LOW Output IOH/IOL
20 µA/−1.2 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
2004 Fairchild Semiconductor Corporation DS009513
74F283

Functional Description

The 74F283 adds two 4-bit binary words A plus B plus the incoming Carry C0 . The binary sum appears on the Sum and outgoing carry C4 outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two.
20 A0 + B0 + C0 + 21 A1 + B1
+ 22 A2 + B2 + 23 A3 + B3
= S0 + 2S1 + 4S2 + 8S3 + 16C4

Where + = plus

Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the 74F283 can be used either with all inputs and outputs active HIGH positive logic or with all inputs and outputs active LOW negative logic . See Figure Note that if C0 is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic.

Due to pin limitations, the intermediate carries of the 74F283 are not brought out for use as inputs or outputs.

However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2 shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder A3, B3 LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the 74F283 into a 2-bit and a 1-bit adder. The third stage adder A2, B2, S2 is used merely as a means of getting a carry C10 signal into the fourth stage via A2 and B2 and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I5 that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs are true, the output M5 is true.

C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4

Logic Levels

L LHLHHL LHHHL LH

Active HIGH
00101100111001

Active LOW
11010011000110

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Datasheet ID: 74F283PC 513312