XR16M2651IL32TR-F

XR16M2651IL32TR-F Datasheet

XR16M2651

Part	Datasheet
XR16M2651IL32TR-F	XR16M2651IL32TR-F (pdf)

Related Parts	Information
XR16M2651IM48TR-F	XR16M2651IM48TR-F

PDF Datasheet Preview
XR16M2651 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE MAY 2007 The XR16M26511 M2651 is a high performance dual universal asynchronous receiver and transmitter UART with 32 byte TX and RX FIFOs. The device operates from to volts and is pin-to-pin and software compatible to the XR16V2551 and XR16L2551. The device includes 2 additional capabilities over the XR16M2650 Intel and Motorola data bus selection and a “PowerSave” mode to minimize the sleep current. It supports Exar’s enhanced features of selectable FIFO trigger level, automatic hardware RTS/CTS and software flow control, and a complete modem interface. An internal loopback capability allows system diagnostics. Independent programmable fractional baud rate generators are provided in each channel to select data rates up to 16 Mbps at Volt with 4X sampling clock. The M2651 is available in 48-pin TQFP and 32pin QFN packages. NOTE 1 Covered by U.S. Patent #5,649,122 • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls • to Volt Operation • Pin-to-pin and software compatible to Exar’s XR16L2551, XR16V2551 and XR16M2551 • Two independent UART channels • Register set is 16550 compatible • Data rate of up to 16 Mbps at V • Data rate of up to Mbps at V • Data rate of up to 8 Mbps at 1.8V • Fractional Baud Rate Generator • Transmit and Receive FIFOs of 32 bytes • Selectable TX and RX FIFO Trigger Levels • Automatic Hardware RTS/CTS Flow Control • Automatic Software Xon/Xoff Flow Control • Wireless Infrared IrDA Encoder/Decoder • Automatic sleep mode with wake-up interrupt • Full modem interface up to 64MHz input • 48-TQFP and 32-QFN packages FIGURE XR16M2651 BLOCK DIAGRAM PwrSave A2:A0 D7:D0 IOR# VCC IOW# R/W# CSA# CS# CSB# A3 INTA IRQ# INTB logic 0 TXRDYA# TXRDYB# RXRDYA# RXRDYB# Reset# 16/68# CLKSEL Intel or Motorola Data Bus Interface UART Channel A UART Regs 32 Byte TX FIFO TX & RX IR ENDEC 32 Byte RX FIFO UART Channel B same as Channel A Crystal Osc/Buffer to 3.63V VCC GND TXA, RXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA#, OP2A# TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B# XTAL1 XTAL2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510 668-7000 • FAX 510 668-7017 • XR16M2651 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE FIGURE PIN OUT ASSIGNMENT 32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 26 VCC 25 CTSA# 32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 26 VCC 25 CTSA# CSA# 7 CSB# 8 XR16M2651 32-pin QFN in 16 Intel Mode 24 RESET ORDERING INFORMATION PART NUMBER XR16M2651IL32 XR16M2651IM48 PACKAGE 32-Pin QFN 48-Lead TQFP OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C DEVICE STATUS Active XR16M2651 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE PIN DESCRIPTIONS Pin Description NAME 32-QFN 48-TQFP TYPE PIN # PIN # DATA BUS INTERFACE IOR# IOW# R/W# CSA# CSB# INTA IRQ# I Address data lines These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. I/O Data bus lines [7:0] bidirectional . I When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe active low . The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC. I When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe active low . The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read HIGH and write LOW signal. I When 16/68# pin is HIGH, this input is chip select A active low to enable channel A in the device. When 16/68# pin is LOW, this input becomes the chip select active low for the Motorola bus interface. I When 16/68# pin is HIGH, this input is chip select B active low to enable channel B in the device. When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects channel B. O When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output active low, open drain . An external pull-up resistor is required for proper operation. XR16M2651 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE Pin Description NAME 32-QFN 48-TQFP TYPE PIN # PIN # INTB O UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW when MCR[3] is set to a logic INTB is set to the three state mode and OP2B# output HIGH when MCR[3] is set to a logic 0 default . See MCR[3]. TXRDYA# - O UART channel A Transmitter Ready active low . The output provides the TX FIFO/ THR status for transmit channel A. See Table If it is not used, leave it uncon- nected. ORDERING 2 FIGURE PIN OUT ASSIGNMENT 2 PIN DESCRIPTIONS 3 PRODUCT 7 FUNCTIONAL 8 CPU 8 FIGURE XR16M2651 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS 8 DEVICE RESET 8 DEVICE IDENTIFICATION AND 9 CHANNEL A AND B 9 TABLE 1 CHANNEL A AND B SELECT IN 16 MODE 9 TABLE 2 CHANNEL A AND B SELECT IN 68 MODE 9 DMA 10 TABLE 3 TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE 10 INTA AND INTB OUTPUTS 10 TABLE 4 INTA AND INTB PINS OPERATION FOR TRANSMITTER 10 TABLE 5 INTA AND INTB PIN OPERATION FOR RECEIVER 10 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT 11 FIGURE TYPICAL CRYSTAL CONNECTIONS 11 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL 11 FIGURE BAUD RATE GENERATOR 12 TABLE 6 TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING 13 TRANSMITTER 13 TRANSMIT HOLDING REGISTER THR - WRITE ONLY 14 TRANSMITTER OPERATION IN NON-FIFO MODE 14 FIGURE TRANSMITTER OPERATION IN NON-FIFO MODE 14 TRANSMITTER OPERATION IN FIFO MODE 14 FIGURE TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE 14 RECEIVER 15 RECEIVE HOLDING REGISTER RHR - READ-ONLY 15 FIGURE RECEIVER OPERATION IN NON-FIFO MODE 15 FIGURE RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE 16 AUTO RTS HARDWARE FLOW CONTROL 16 AUTO RTS 17 TABLE 7 AUTO RTS HARDWARE FLOW CONTROL 17 AUTO CTS FLOW CONTROL 17 FIGURE AUTO RTS AND CTS FLOW CONTROL 18 AUTO XON/XOFF SOFTWARE FLOW 19 TABLE 8 AUTO XON/XOFF SOFTWARE FLOW CONTROL 19 SPECIAL CHARACTER DETECT 19 INFRARED MODE 20 FIGURE INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING 20 SLEEP MODE WITH WAKE-UP INDICATOR AND POWERSAVE 21 SLEEP MODE 21 POWERSAVE 21 INTERNAL LOOPBACK 22 FIGURE INTERNAL LOOP BACK IN CHANNEL A AND B 22 UART INTERNAL REGISTERS 23 TABLE 9 UART CHANNEL A AND B UART INTERNAL REGISTERS 23 TABLE 10 INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 24 INTERNAL REGISTER 25 RECEIVE HOLDING REGISTER RHR - READ- ONLY 25 TRANSMIT HOLDING REGISTER THR - WRITE-ONLY 25 INTERRUPT ENABLE REGISTER IER - 25 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION 25 XR16M2651 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE 26 INTERRUPT STATUS REGISTER ISR - READ-ONLY 27 INTERRUPT GENERATION 27 INTERRUPT CLEARING 27 TABLE 11 INTERRUPT SOURCE AND PRIORITY LEVEL 28

PDF Datasheet Preview

XR16M2651

HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE

MAY 2007

The XR16M26511 M2651 is a high performance dual universal asynchronous receiver and transmitter UART with 32 byte TX and RX FIFOs. The device operates from to volts and is pin-to-pin and software compatible to the XR16V2551 and XR16L2551. The device includes 2 additional capabilities over the XR16M2650 Intel and Motorola data bus selection and a “PowerSave” mode to minimize the sleep current. It supports Exar’s enhanced features of selectable FIFO trigger level, automatic hardware RTS/CTS and software flow control, and a complete modem interface. An internal loopback capability allows system diagnostics. Independent programmable fractional baud rate generators are provided in each channel to select data rates up to 16 Mbps at Volt with 4X sampling clock. The M2651 is available in 48-pin TQFP and 32pin QFN packages.

NOTE 1 Covered by U.S. Patent #5,649,122
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
• to Volt Operation
• Pin-to-pin and software compatible to Exar’s

XR16L2551, XR16V2551 and XR16M2551
• Two independent UART channels
• Register set is 16550 compatible
• Data rate of up to 16 Mbps at V
• Data rate of up to Mbps at V
• Data rate of up to 8 Mbps at 1.8V
• Fractional Baud Rate Generator
• Transmit and Receive FIFOs of 32 bytes
• Selectable TX and RX FIFO Trigger Levels
• Automatic Hardware RTS/CTS Flow Control
• Automatic Software Xon/Xoff Flow Control
• Wireless Infrared IrDA Encoder/Decoder
• Automatic sleep mode with wake-up interrupt
• Full modem interface
up to 64MHz input
• 48-TQFP and 32-QFN packages

FIGURE XR16M2651 BLOCK DIAGRAM

PwrSave

A2:A0 D7:D0 IOR# VCC IOW# R/W# CSA# CS# CSB# A3 INTA IRQ# INTB logic 0

TXRDYA# TXRDYB# RXRDYA# RXRDYB#

Reset# 16/68# CLKSEL

Intel or Motorola Data Bus Interface

UART Channel A

UART Regs
32 Byte TX FIFO

TX & RX

IR ENDEC
32 Byte RX FIFO

UART Channel B same as Channel A

Crystal Osc/Buffer
to 3.63V VCC GND

TXA, RXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA#, OP2A#

TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B# XTAL1 XTAL2

Exar Corporation 48720 Kato Road, Fremont CA, 94538
• 510 668-7000
• FAX 510 668-7017
•

XR16M2651

HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE FIGURE PIN OUT ASSIGNMENT
32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 26 VCC 25 CTSA#
32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 26 VCC 25 CTSA#

CSA# 7 CSB# 8

XR16M2651 32-pin QFN in 16 Intel Mode
24 RESET
ORDERING INFORMATION

PART NUMBER XR16M2651IL32 XR16M2651IM48

PACKAGE 32-Pin QFN 48-Lead TQFP

OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C

DEVICE STATUS Active

XR16M2651

HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE

PIN DESCRIPTIONS

Pin Description

NAME
32-QFN 48-TQFP TYPE

PIN # PIN #

DATA BUS INTERFACE

IOR#

IOW#

R/W#

CSA#

CSB#

INTA

IRQ#

I Address data lines These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction.

I/O Data bus lines [7:0] bidirectional .

I When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe active low . The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC.

I When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe active low . The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read HIGH and write LOW signal.

I When 16/68# pin is HIGH, this input is chip select A active low to enable channel A in the device. When 16/68# pin is LOW, this input becomes the chip select active low for the Motorola bus interface.

I When 16/68# pin is HIGH, this input is chip select B active low to enable channel B in the device. When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects channel B.

O When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output active low, open drain . An external pull-up resistor is required for proper operation.

XR16M2651

HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE Pin Description

NAME
32-QFN 48-TQFP TYPE

PIN # PIN #

INTB

O UART channel B Interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTB is set to the active mode and OP2B# output

LOW when MCR[3] is set to a logic INTB is set to the three state mode and

OP2B# output HIGH when MCR[3] is set to a logic 0 default . See MCR[3].

TXRDYA# -

O UART channel A Transmitter Ready active low . The output provides the TX FIFO/

THR status for transmit channel A. See Table If it is not used, leave it uncon-
nected.
ORDERING 2

FIGURE PIN OUT ASSIGNMENT 2

PIN DESCRIPTIONS 3

PRODUCT 7 FUNCTIONAL 8

CPU 8

FIGURE XR16M2651 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS 8

DEVICE RESET 8 DEVICE IDENTIFICATION AND 9 CHANNEL A AND B 9

TABLE 1 CHANNEL A AND B SELECT IN 16 MODE 9 TABLE 2 CHANNEL A AND B SELECT IN 68 MODE 9

DMA 10

TABLE 3 TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE 10

INTA AND INTB OUTPUTS 10

TABLE 4 INTA AND INTB PINS OPERATION FOR TRANSMITTER 10 TABLE 5 INTA AND INTB PIN OPERATION FOR RECEIVER 10

CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT 11

FIGURE TYPICAL CRYSTAL CONNECTIONS 11

PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL 11

FIGURE BAUD RATE GENERATOR 12 TABLE 6 TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING 13

TRANSMITTER 13

TRANSMIT HOLDING REGISTER THR - WRITE ONLY 14 TRANSMITTER OPERATION IN NON-FIFO MODE 14 FIGURE TRANSMITTER OPERATION IN NON-FIFO MODE 14 TRANSMITTER OPERATION IN FIFO MODE 14 FIGURE TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE 14

RECEIVER 15

RECEIVE HOLDING REGISTER RHR - READ-ONLY 15 FIGURE RECEIVER OPERATION IN NON-FIFO MODE 15 FIGURE RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE 16

AUTO RTS HARDWARE FLOW CONTROL 16 AUTO RTS 17

TABLE 7 AUTO RTS HARDWARE FLOW CONTROL 17

AUTO CTS FLOW CONTROL 17

FIGURE AUTO RTS AND CTS FLOW CONTROL 18

AUTO XON/XOFF SOFTWARE FLOW 19

TABLE 8 AUTO XON/XOFF SOFTWARE FLOW CONTROL 19

SPECIAL CHARACTER DETECT 19 INFRARED MODE 20

FIGURE INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING 20

SLEEP MODE WITH WAKE-UP INDICATOR AND POWERSAVE 21

SLEEP MODE 21 POWERSAVE 21

INTERNAL LOOPBACK 22

FIGURE INTERNAL LOOP BACK IN CHANNEL A AND B 22

UART INTERNAL REGISTERS 23

TABLE 9 UART CHANNEL A AND B UART INTERNAL REGISTERS 23 TABLE 10 INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 24

INTERNAL REGISTER 25 RECEIVE HOLDING REGISTER RHR - READ- ONLY 25 TRANSMIT HOLDING REGISTER THR - WRITE-ONLY 25 INTERRUPT ENABLE REGISTER IER - 25

IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION 25

XR16M2651

HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE

IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE 26

INTERRUPT STATUS REGISTER ISR - READ-ONLY 27

INTERRUPT GENERATION 27 INTERRUPT CLEARING 27 TABLE 11 INTERRUPT SOURCE AND PRIORITY LEVEL 28

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived XR16M2651IL32TR-F Datasheet file may be downloaded here without warranties.

Datasheet ID: XR16M2651IL32TR-F 512919