74F191SJX

74F191SJX Datasheet


74F191 Up/Down Binary Counter with Preset and Ripple Clock

Part Datasheet
74F191SJX 74F191SJX 74F191SJX (pdf)
Related Parts Information
74F191PC 74F191PC 74F191PC
74F191SC 74F191SC 74F191SC
74F191SJ 74F191SJ 74F191SJ
74F191SCX 74F191SCX 74F191SCX
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74F191 Up/Down Binary Counter with Preset and Ripple Clock

April 2007
74F191 tm

Up/Down Binary Counter with Preset and Ripple Clock
• typical count frequency
• Synchronous counting
• Asynchronous parallel load
• Cascadable
Ordering Information

Order Number 74F191SC 74F191SJ 74F191PC

Package Number

M16A M16D N16E

Package Description 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Logic Symbols

Connection Diagram

IEEE/IEC
74F191 Up/Down Binary Counter with Preset and Ripple Clock

Unit Loading/Fan Out

Pin Names CE CP PL U/D RC TC

Description Count Enable Input Active LOW Clock Pulse Input Active Rising Edge Parallel Data Inputs Asynchronous Parallel Load Input Active LOW Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output Active LOW Terminal Count Output Active HIGH

U.L. HIGH / LOW
/ / / / / 50 / 50 / 50 /

Input IIH / IIL Output IOH / IOL
20µA / -1.8mA 20µA / mA 20µA / mA 20µA / -0.6mA 20µA / -0.6mA -1mA / 20mA -1mA / 20mA -1mA / 20mA

Functional Description

The 74F191 is a synchronous up/down 4-bit binary counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations.

Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load PL input is LOW, information present on the Parallel Data inputs is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table.

A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed.

Two types of outputs are provided as overflow/underflow indicators. The Terminal Count TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches 15 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes.

The TC signal is also used internally to enable the Ripple Clock RC output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies
the design of multistage counters, as indicated in Figure 1 and Figure In Figure 1, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages.

A method of causing state changes to occur simultaneously in all stages is shown in Figure All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH.

The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figure 1 and Figure 2 doesn’t apply, because the TC output of a given stage is not affected by its own CE.
1988 Fairchild Semiconductor Corporation
74F191 Up/Down Binary Counter with Preset and Ripple Clock

Mode Select Table

Inputs

PL CE U/D CP

Mode

Count Up

Count Down

X Preset Asyn.

H X No Change Hold

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Clock Transition = LOW Pulse

RC Truth Table

Inputs

Note TC is generated internally.

Output RC

Figure n-Stage Counter Using Ripple Clock

Figure Synchronous n-Stage Counter Using Ripple Carry/Borrow

Figure Synchronous n-Stage Counter with Gated Carry/Borrow
1988 Fairchild Semiconductor Corporation
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Datasheet ID: 74F191SJX 513296