74F190PC

74F190PC Datasheet

74F190 Up/Down Decade Counter with Preset and Ripple Clock

Part	Datasheet
74F190PC	74F190PC (pdf)

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74F190 Up/Down Decade Counter with Preset and Ripple Clock 74F190 Up/Down Decade Counter with Preset and Ripple Clock s MHz typical count frequency s Synchronous counting s Asynchronous parallel load s Cascadable Ordering Code: Order Number Package Number Package Description 74F190SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F190PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 1999 Fairchild Semiconductor Corporation DS009494 74F190 Unit Loading/Fan Out Pin Names CE CP PL U/D RC TC Count Enable Input Active LOW Clock Pulse Input Active Rising Edge Parallel Data Inputs Asynchronous Parallel Load Input Active LOW Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output Active LOW Terminal Count Output Active HIGH U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−1.8 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA Functional Description The 74F190 is a synchronous up/down BCD decade counter containing four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. It has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load PL input is LOW, information present on the Parallel Data inputs is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOWto-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table, CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches 9 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock RC output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi- stage counters. For a discussion and illustrations of the various methods of implementing multistage counters, please see the 74F191 data sheet. RC Truth Table Inputs TC* H Output Mode Select Table Inputs U/D L H *TC is generated internally H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition = LOW Pulse Mode Count Up Count Down Preset Asyn. No Change Hold 74F190 State Diagram Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F190 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2

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74F190 Up/Down Decade Counter with Preset and Ripple Clock
74F190 Up/Down Decade Counter with Preset and Ripple Clock
s MHz typical count frequency s Synchronous counting s Asynchronous parallel load s Cascadable
Ordering Code:

Order Number Package Number

Package Description
74F190SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F190PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
1999 Fairchild Semiconductor Corporation DS009494
74F190

Unit Loading/Fan Out

Pin Names

CE CP PL U/D RC TC

Count Enable Input Active LOW Clock Pulse Input Active Rising Edge Parallel Data Inputs Asynchronous Parallel Load Input Active LOW Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output Active LOW Terminal Count Output Active HIGH

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−1.8 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

The 74F190 is a synchronous up/down BCD decade counter containing four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. It has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load PL input is LOW, information present on the Parallel Data inputs is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOWto-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table, CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed.

Two types of outputs are provided as overflow/underflow indicators. The Terminal Count TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches 9 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock RC output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi-
stage counters. For a discussion and illustrations of the various methods of implementing multistage counters, please see the 74F191 data sheet.

RC Truth Table

Inputs

TC* H

Output

Mode Select Table

Inputs

U/D L H
*TC is generated internally H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Clock Transition = LOW Pulse

Mode

Count Up Count Down Preset Asyn. No Change Hold
74F190

State Diagram Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F190

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2

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Datasheet ID: 74F190PC 513293