74F182PC

74F182PC Datasheet

74F182 Carry Lookahead Generator

Part	Datasheet
74F182PC	74F182PC (pdf)

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74F182 Carry Lookahead Generator 74F182 Carry Lookahead Generator The 74F182 is a high-speed carry lookahead generator. It is generally used with the 74F181 or 74F381 4-bit arithmetic logic units to provide high-speed lookahead over word lengths of more than four bits. s Provides lookahead carries across a group of four ALUs s Multi-level lookahead high-speed arithmetic operation over long word lengths Ordering Code: Order Number Package Number Package Description 74F182SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F182PC Note 1 N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1 This device not available in Tape and Reel. Logic Symbols Connection Diagram 2002 Fairchild Semiconductor Corporation DS009492 74F182 Unit Loading/Fan Out Pin Names Cn G0, G2 G1 G3 P0, P1 P2 P3 Cn+x − Cn+z G Carry Input Carry Generate Inputs Active LOW Carry Generate Input Active LOW Carry Generate Input Active LOW Carry Propagate Inputs Active LOW Carry Propagate Input Active LOW Carry Propagate Input Active LOW Carry Outputs Carry Generate Output Active LOW Carry Propagate Output Active LOW U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−1.2 mA 20 µA/−8.4 mA 20 µA/−9.6 mA 20 µA/−4.8 mA 20 µA/−4.8 mA 20 µA/−3.6 mA 20 µA/−2.4 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA Functional Description The 74F182 carry lookahead generator accepts up to four pairs of Active LOW Carry Propagate and Carry Generate signals and an Active HIGH Carry input Cn and provides anticipated Active HIGH carries Cn + x, Cn+y, Cn+z across four groups of binary adders. The 74F182 also has Active LOW Carry Propagate P and Carry Generate G outputs which may be used for further levels of lookahead. The logic equations provided at the outputs are: Cn+x = G0 + P0 Cn+y = G1 + P1 G0 + P1 P0 Cn+z = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 Cn G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 P = P2 P1 P0 Also, the 74F182 can be used with binary ALUs in an active LOW or active HIGH input operand mode. The connections Figure 1 to and from the ALU to the carry lookahead generator are identical in both cases. Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by dropping the last 74F181 or 74F381. *ALUs may be either 74F181 or 74F381 FIGURE 32-Bit ALU with Rippled Carry between 16-Bit Lookahead ALUs 74F182 Truth Table Inputs Outputs Cn G0 P0 G1 P1 G2 P2 G3 P3 Cn+x Cn+y Cn+z G XXXHH XHHHX LHXHX XXXLX XLXXL HX L X L XXXHHHX XHHHXHX LHXHXHX XXXLXXL XLXXLXL HX L X L X L XXXXHH XXHHHX HHHXHX HXHXHX XXXXLX XXLXXL

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74F182 Carry Lookahead Generator
74F182 Carry Lookahead Generator

The 74F182 is a high-speed carry lookahead generator. It is generally used with the 74F181 or 74F381 4-bit arithmetic logic units to provide high-speed lookahead over word lengths of more than four bits.
s Provides lookahead carries across a group of four ALUs s Multi-level lookahead high-speed arithmetic operation
over long word lengths
Ordering Code:

Order Number Package Number

Package Description
74F182SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F182PC Note 1

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1 This device not available in Tape and Reel.

Logic Symbols

Connection Diagram
2002 Fairchild Semiconductor Corporation DS009492
74F182

Unit Loading/Fan Out

Pin Names

Cn G0, G2 G1 G3 P0, P1 P2 P3 Cn+x − Cn+z G

Carry Input Carry Generate Inputs Active LOW Carry Generate Input Active LOW Carry Generate Input Active LOW Carry Propagate Inputs Active LOW Carry Propagate Input Active LOW Carry Propagate Input Active LOW Carry Outputs Carry Generate Output Active LOW Carry Propagate Output Active LOW

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−1.2 mA 20 µA/−8.4 mA 20 µA/−9.6 mA 20 µA/−4.8 mA 20 µA/−4.8 mA 20 µA/−3.6 mA 20 µA/−2.4 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

The 74F182 carry lookahead generator accepts up to four pairs of Active LOW Carry Propagate and Carry Generate signals and an Active HIGH Carry input Cn and provides anticipated Active HIGH carries Cn + x, Cn+y, Cn+z across four groups of binary adders. The 74F182 also has Active LOW Carry Propagate P and Carry Generate G outputs which may be used for further levels of lookahead. The logic equations provided at the outputs are:

Cn+x = G0 + P0 Cn+y = G1 + P1 G0 + P1 P0 Cn+z = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 Cn G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0

P = P2 P1 P0

Also, the 74F182 can be used with binary ALUs in an active LOW or active HIGH input operand mode. The connections Figure 1 to and from the ALU to the carry lookahead generator are identical in both cases. Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by dropping the last 74F181 or 74F381.
*ALUs may be either 74F181 or 74F381

FIGURE 32-Bit ALU with Rippled Carry between 16-Bit Lookahead ALUs
74F182

Truth Table

Inputs

Outputs

Cn G0 P0 G1 P1 G2 P2 G3 P3 Cn+x Cn+y Cn+z G

XXXHH

XHHHX

LHXHX

XXXLX

XLXXL

HX L X L

XXXHHHX

XHHHXHX

LHXHXHX

XXXLXXL

XLXXLXL

HX L X L X L

XXXXHH

XXHHHX

HHHXHX

HXHXHX

XXXXLX

XXLXXL

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Datasheet ID: 74F182PC 513291