74F112SJX

74F112SJX Datasheet

74F112 Dual JK Negative Edge-Triggered Flip-Flop

Part	Datasheet
74F112SJX	74F112SJX (pdf)

Related Parts	Information
74F112SCX	74F112SCX
74F112SC	74F112SC
74F112SJ	74F112SJ
74F112PC	74F112PC

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74F112 Dual JK Negative Edge-Triggered Flip-Flop 74F112 Dual JK Negative Edge-Triggered Flip-Flop The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F112SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F112SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F112PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009472 74F112 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL J1, J2, K1, K2 Data Inputs CP1, CP2 Clock Pulse Inputs Active Falling Edge CD1, CD2 Direct Clear Inputs Active LOW SD1, SD2 Direct Set Inputs Active LOW Q1, Q2, Q1, Q2 Outputs 20 µA/−0.6 mA 20 µA/−2.4 mA 20 µA/−3.0 mA 20 µA/−3.0 mA −1 mA/20 mA Truth Table Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = HIGH-to-LOW Clock Transition Q0 = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram One Half Shown Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F112 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output

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74F112 Dual JK Negative Edge-Triggered Flip-Flop
74F112 Dual JK Negative Edge-Triggered Flip-Flop

The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively.

Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs:

LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q
and Q HIGH
Ordering Code:

Order Number Package Number

Package Description
74F112SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F112SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F112PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009472
74F112

Unit Loading/Fan Out

Pin Names

U.L.

Input IIH/IIL

HIGH/LOW Output IOH/IOL

J1, J2, K1, K2 Data Inputs

CP1, CP2

Clock Pulse Inputs Active Falling Edge

CD1, CD2

Direct Clear Inputs Active LOW

SD1, SD2

Direct Set Inputs Active LOW

Q1, Q2, Q1, Q2 Outputs
20 µA/−0.6 mA 20 µA/−2.4 mA 20 µA/−3.0 mA 20 µA/−3.0 mA −1 mA/20 mA

Truth Table

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = HIGH-to-LOW Clock Transition Q0 = Before HIGH-to-LOW Transition of Clock

Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.

Logic Diagram

One Half Shown

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F112

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output

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Datasheet ID: 74F112SJX 513268