74F174SJ
74F174SJ Datasheet
74F174 Hex D-Type Flip-Flop with Master Reset
| Part | Datasheet |
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74F174SJ |
74F174SJ (pdf) |
| Related Parts | Information |
|---|---|
74F174SJX |
74F174SJX |
74F174SCX |
74F174SCX |
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74F174SC |
74F174SC |
74F174PC |
74F174PC |
| PDF Datasheet Preview |
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| 74F174 Hex D-Type Flip-Flop with Master Reset 74F174 Hex D-Type Flip-Flop with Master Reset The 74F174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s Asynchronous common reset s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number Package Number Package Description 74F174SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F174SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F174PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009489 74F174 Unit Loading/Fan Out Pin Names CP MR Data Inputs Clock Pulse Input Active Rising Edge Master Reset Input Active LOW Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 74F174 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock CP and Master Reset MR are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock CP transition. A LOW input to the Master Reset MR will force all outputs LOW independent of Clock or Data inputs. The 74F174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Clock Transition Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F174 Absolute Maximum Ratings Note 1 Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output Current Applied to Output in LOW State Max ESD Last Passing Voltage Min −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to mA −0.5V to VCC −0.5V to +5.5V twice the rated IOL mA 4000V Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2 Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Parameter Units Conditions Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage |
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