74F138SJ

74F138SJ Datasheet

74F138 1-of-8 Decoder/Demultiplexer

Part	Datasheet
74F138SJ	74F138SJ (pdf)

Related Parts	Information
74F138PC	74F138PC
74F138SC	74F138SC
74F138SJX	74F138SJX
74F138SCX	74F138SCX

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74F138 1-of-8 Decoder/Demultiplexer 74F138 1-of-8 Decoder/Demultiplexer The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using four F138 devices and one inverter. s Demultiplexing capability s Multiple input enable for easy expansion s Active LOW mutually exclusive outputs Ordering Code: Order Number Package Number Package Description 74F138SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F138SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F138PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009478 74F138 Unit Loading/Fan Out Pin Names E1, E2 E3 Address Inputs Enable Inputs Active LOW Enable Input Active HIGH Outputs Active LOW Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Functional Description The F138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs A0, A1, A2 and, when enabled, provides eight mutually exclusive active LOW outputs The F138 features three Enable inputs, two active LOW E1, E2 and one active HIGH E3 . All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Outputs expansion of the device to a 1-of-32 5 lines to 32 lines decoder with just four F138 devices and one inverter See Figure The F138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW state. FIGURE Expansion to 1-of-32 Decoding 2 74F138 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F138 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA

PDF Datasheet Preview

74F138 1-of-8 Decoder/Demultiplexer
74F138 1-of-8 Decoder/Demultiplexer

The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using four F138 devices and one inverter.
s Demultiplexing capability s Multiple input enable for easy expansion s Active LOW mutually exclusive outputs
Ordering Code:

Order Number Package Number

Package Description
74F138SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F138SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F138PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009478
74F138

Unit Loading/Fan Out

Pin Names

E1, E2 E3

Address Inputs Enable Inputs Active LOW Enable Input Active HIGH Outputs Active LOW

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Functional Description

The F138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs A0, A1, A2 and, when enabled, provides eight mutually exclusive active LOW outputs The F138 features three Enable inputs, two active LOW E1, E2 and one active HIGH E3 . All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA

Outputs
expansion of the device to a 1-of-32 5 lines to 32 lines decoder with just four F138 devices and one inverter See Figure The F138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW state.

FIGURE Expansion to 1-of-32 Decoding 2
74F138

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F138

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

More datasheets: 74F399SC | 74F399SJX | 74F399SCX | 74F399SJ | FQD6N60CTM | FQD6N60CTM-WS | 17000185A | 390-1261 | 74F138PC | 74F138SC

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Datasheet ID: 74F138SJ 513274