74F399SJ

74F399SJ Datasheet

74F399 Quad 2-Port Register

Part	Datasheet
74F399SJ	74F399SJ (pdf)

Related Parts	Information
74F399PC	74F399PC
74F399SC	74F399SC
74F399SJX	74F399SJX
74F399SCX	74F399SCX

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74F399 Quad 2-Port Register 74F399 Quad 2-Port Register The 74F399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flops on the rising edge of the clock. s Select inputs from two data sources s Fully positive edge-triggered operation Ordering Code: Order Number Package Number Package Description 74F399SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F399SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F399PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Unit Loading/Fan Out Pin Names Common Select Input Clock Pulse Input Active Rising Edge Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs 2004 Fairchild Semiconductor Corporation DS009533 U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA 74F399 Functional Description The 74F399 is a high-speed quad 2-port registers. They select four bits of data from either of two sources Ports under control of a common Select input S . The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input CP . The 4-bit D-type output register is fully edge-triggered. The Data inputs I0x, I1x and Select input S must be stable only a setup time prior to and hold time after the LOW-toHIGH transition of the Clock input for predictable operation. Logic Diagram Function Table Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial *F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F399 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max ESD Last Passing Voltage twice the rated IOL mA 4000V Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage

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74F399 Quad 2-Port Register
74F399 Quad 2-Port Register

The 74F399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flops on the rising edge of the clock.
s Select inputs from two data sources s Fully positive edge-triggered operation
Ordering Code:

Order Number Package Number

Package Description
74F399SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F399SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F399PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

Unit Loading/Fan Out

Pin Names

Common Select Input Clock Pulse Input Active Rising Edge Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs
2004 Fairchild Semiconductor Corporation DS009533

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA
74F399

Functional Description

The 74F399 is a high-speed quad 2-port registers. They select four bits of data from either of two sources Ports under control of a common Select input S . The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input CP . The 4-bit D-type output register is fully edge-triggered. The Data inputs I0x, I1x and Select input S must be stable only a setup time prior to and hold time after the LOW-toHIGH transition of the Clock input for predictable operation.

Logic Diagram

Function Table

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH
clock transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH
clock transition X = Immaterial
*F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F399

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max ESD Last Passing Voltage
twice the rated IOL mA
4000V

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage

More datasheets: ATA6833C-PLQW | FJN4303RBU | 5644H5 | 5644H1 | 5644H7 | EIR508-T | 74F399PC | 74F399SC | 74F399SJX | 74F399SCX

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Datasheet ID: 74F399SJ 513333