74F113PC

74F113PC Datasheet

74F113 Dual JK Negative Edge-Triggered Flip-Flop

Part	Datasheet
74F113PC	74F113PC (pdf)

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74F113 Dual JK Negative Edge-Triggered Flip-Flop 74F113 Dual JK Negative Edge-Triggered Flip-Flop The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Asynchronous input: LOW input to SD sets Q to HIGH level Set is independent of clock Ordering Code: Order Number Package Number Package Description 74F113SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow 74F113SJ M14D 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F113PC N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009473 74F113 Unit Loading/Fan Out Pin Names J1, J2, K1, K2 CP1, CP2 SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs Active Falling Edge Direct Set Inputs Active LOW Outputs Truth Table U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−2.4 mA 20 µA/−3.0 mA −1 mA/20 mA Inputs Outputs H = HIGH Voltage Level l = LOW Voltage level ] = HIGH-to-LOW Clock Transition X = Immaterial Q0 = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition. Logic Diagram One Half Shown Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F113 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage

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74F113 Dual JK Negative Edge-Triggered Flip-Flop
74F113 Dual JK Negative Edge-Triggered Flip-Flop

The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is
transferred to the outputs on the falling edge of the clock pulse. Asynchronous input:

LOW input to SD sets Q to HIGH level Set is independent of clock
Ordering Code:

Order Number Package Number

Package Description
74F113SC

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow
74F113SJ

M14D
14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F113PC

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009473
74F113

Unit Loading/Fan Out

Pin Names

J1, J2, K1, K2 CP1, CP2 SD1, SD2 Q1, Q2, Q1, Q2

Data Inputs Clock Pulse Inputs Active Falling Edge Direct Set Inputs Active LOW Outputs

Truth Table

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−2.4 mA 20 µA/−3.0 mA −1 mA/20 mA

Inputs

Outputs

H = HIGH Voltage Level
l = LOW Voltage level
] = HIGH-to-LOW Clock Transition X = Immaterial Q0 = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition.

Logic Diagram

One Half Shown

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F113

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage

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Datasheet ID: 74F113PC 513269