74ALVC16821MTD

74ALVC16821MTD Datasheet

74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs

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74ALVC16821MTD	74ALVC16821MTD (pdf)

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74ALVC16821MTDX	74ALVC16821MTDX

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74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs 74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs The ALVC16821 contains twenty non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The 74ALVC16821 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V. The 74ALVC16821 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s VCC supply operation s 3.6V tolerant inputs and outputs s tPD ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Descriptions 74ALVC16821MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn CLKn Output Enable Input Active LOW Clock Input Inputs Outputs 2001 Fairchild Semiconductor Corporation DS500685 74ALVC16821 Connection Diagram Logic Diagrams Truth Tables Inputs Outputs CLK1 L or H Inputs Outputs CLK2 L or H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance = Previous O0 before LOW-to-HIGH transition of Clock = LOW-to-HIGH transition Functional Description The 74ALVC16821 contains twenty D-type flip-flops with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of each other. Control pins can be shorted together to obtain full 20-bit operation. The following description applies to each byte. The twenty flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CLK transition. The 3-STATE standard outputs are controlled by the Output Enable OEn input. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the flip-flops. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ALVC16821 Absolute Maximum Ratings Note 2 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 4 Power Supply Operating 1.65V to 3.6V Input Voltage VI Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate

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74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs

The ALVC16821 contains twenty non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications.

The 74ALVC16821 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

The 74ALVC16821 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s VCC supply operation s 3.6V tolerant inputs and outputs s tPD
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Descriptions
74ALVC16821MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

OEn CLKn

Output Enable Input Active LOW Clock Input Inputs Outputs
2001 Fairchild Semiconductor Corporation DS500685
74ALVC16821

Connection Diagram Logic Diagrams

Truth Tables

Inputs

Outputs

CLK1

L or H

Inputs

Outputs

CLK2

L or H

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance
= Previous O0 before LOW-to-HIGH transition of Clock = LOW-to-HIGH transition

Functional Description

The 74ALVC16821 contains twenty D-type flip-flops with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of each other. Control pins can be shorted together to obtain full 20-bit operation. The following description applies to each byte. The twenty flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CLK transition. The 3-STATE standard outputs are controlled by the Output Enable OEn input. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the flip-flops.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ALVC16821

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 4

Power Supply

Operating
1.65V to 3.6V

Input Voltage VI Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate

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Datasheet ID: 74ALVC16821MTD 513241