74ACTQ18823MTD

74ACTQ18823MTD Datasheet


74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs

Part Datasheet
74ACTQ18823MTD 74ACTQ18823MTD 74ACTQ18823MTD (pdf)
Related Parts Information
74ACTQ18823SSC 74ACTQ18823SSC 74ACTQ18823SSC
74ACTQ18823MTDX 74ACTQ18823MTDX 74ACTQ18823MTDX
74ACTQ18823SSCX 74ACTQ18823SSCX 74ACTQ18823SSCX
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74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs

The ACTQ18823 contains eighteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP , Clear CLR , Clock Enable EN and Output Enable OE are common to each byte and can be shorted together for full 18-bit operation.

The ACTQ18823 utilizes Fairchild’s Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector for superior performance.
s Utilizes Fairchild’s FACT Quiet Series technology s Broadside pinout allows for easy board layout s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s Extra data width for wider address/data paths or buses
carrying parity s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:

Order Number Package Number

Package Description
74ACTQ18823SSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74ACTQ18823MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

OEn CLRn ENn CPn

Description Output Enable Input Active LOW Clear Active LOW Clock Enable Active LOW Clock Pulse Input Inputs Outputs

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010953
74ACTQ18823

Connection Diagram

Functional Description

The ACTQ18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. The buffered clock CPn and buffered Output Enable OEn are common to all flip-flops within that byte. The flip-flops will store the state of their individual D inputs that meet set-up and hold time requirements on the LOW-to-HIGH CPn transition. With OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the impedance state. Operation of the OEn input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear CLRn and Clock Enable ENn pins. These devices are ideal for parity bus interfacing in high performance systems.

When CLRn is LOW and OEn is LOW, the outputs are LOW. When CLRn is HIGH, data can be entered into the flip-flops. When ENn is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the ENn is HIGH, the outputs do not change state, regardless of the data or clock input transitions.

Function Table Note 1

Inputs

Internal

Output

H= HIGH Voltage Level L= LOW Voltage Level X= Immaterial

High Impedance = LOW-to-HIGH Transition NC= No Change

Note 1 The table represents the logic for one byte. The two bytes are independent of each other and function identically.

Function

High Z High Z Clear Hold Load
74ACTQ18823

Logic Diagrams

Byte 1 0:8

Byte 2 9:17
74ACTQ18823

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC +0.5V DC Output Diode Current IOK VO = −0.5V VO = VCC +0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current Per Output Pin

Junction Temperature

PDIP/SOIC

Storage Temperature

ESD Last Passing Voltage Min
−0.5V to +7.0V
−20 mA +20 mA
−20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA
± 50 mA
+140°C −65°C to +150°C
4000V

Recommended Operating Conditions
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Datasheet ID: 74ACTQ18823MTD 513205