AS4C64M8D3-12BIN

AS4C64M8D3-12BIN Datasheet

AS4C64M8D3-12BIN AS4C64M8D3-12BCN

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AS4C64M8D3-12BIN AS4C64M8D3-12BCN Date Aug. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 84 - AS4C64M8D3-12BIN AS4C64M8D3-12BCN 64M x 8 bit DDR3 Synchronous DRAM SDRAM • JEDEC Standard Compliant • Power supplies VDD & VDDQ = +1.5V 0.075V • Operating temperature range: - Commercial TC = 0~95°C - Industrial TC = -40~95°C • Supports JEDEC clock jitter specification • Fully synchronous operation • Fast clock rate 800MHz • Differential Clock, CK & CK# • Bidirectional differential data strobe - DQS & DQS# • 8 internal banks for concurrent operation • 8n-bit prefetch architecture • Pipelined internal architecture • Precharge & active power down • Programmable Mode & Extended Mode registers • Additive Latency AL 0, CL-1, CL-2 • Programmable Burst lengths 4, 8 • Burst type Sequential / Interleave • Output Driver Impedance Control • 8192 refresh cycles / 64ms - Average refresh period 7.8us -40°C +85°C 3.9us +85°C +95°C • Write Leveling • ZQ Calibration • Dynamic ODT Rtt_Nom & Rtt_WR • RoHS compliant • Auto Refresh and Self Refresh • 78-ball 8 x 1.0mm FBGA package - Pb and Halogen Free Overview The 512Mb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 512Mb chip is organized as 8Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks CK rising and CK# falling . All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ±0.075V power supply and are available in BGA packages. Table Ordering Information Product part No Temperature Max Clock MHz AS4C64M8D3-12BCN 64M x 8 Commercial 0°C to 95°C AS4C64M8D3-12BIN 64M x 8 Industrial -40°C to 95°C Package 78-ball FBGA 78-ball FBGA Table Speed Grade Information Speed Grade Clock Frequency CAS Latency DDR3-1600 800 MHz tRCD ns tRP ns Confidential - 2 of 84 - AS4C64M8D3-12BIN AS4C64M8D3-12BCN Figure Ball Assignment FBGA Top View TDQS# VSSQ TDQS VDDQ VSS VSSQ DQ3 VDD VDDQ VSSQ VSSQ DQS# VSSQ VREFDQ VDDQ VDDQ RAS# CAS# A10/AP VREFCA A12/BC# VSS RESET# Confidential - 3 of 84 - Figure Block Diagram CK# CKE DLL CLOCK BUFFER RESET# CS# Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC# Table Burst Type and Burst Order Burst Length Read Write Starting Column Address A2 A1 A0 Sequential A3=0 Interleave A3=1 Note 0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T 0 1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T 0 1 0 2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T Read 3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 1, 2, 3 Chop 1 0 1 5, 6, 7, 4, T, T, T, T 5, 4, 7, 6, T, T, T, T 1 0 6, 7, 4, 5, T, T, T, T 6, 7, 4, 5, T, T, T, T 1 7, 4, 5, 6, T, T, T, T 7, 6, 5, 4, T, T, T, T Write 0 V 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 1, 2, 4, 1 V 4, 5, 6, 7, X, X, X, X 4, 5, 6, 7, X, X, X, X 5 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 Read 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 Write V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2, 4 Note: In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks. 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst. T Output driver for data and strobes are in high impedance. V a valid logic level 0 or 1 , but respective buffer input ignores level on input pins. One bit wide logical interface via all DQ pins during READ operation. Register Read on x8 DQL[0] drive information from MPR. DQL[7:1] either drive the same information as DQL [0], or they drive 0b. Addressing during for Multi Purpose Register reads for all MPR agents BA [2:0] don‟t care A[1:0] A[1:0] must be equal to "00"b. Data read burst order in nibble is fixed A[2] For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], * For Burst Chop 4 cases, the burst order is switched on nibble base A [2]=0b, Burst order 0,1,2,3 * A[2]=1b, Burst order 4,5,6,7 * A[9:3] don‟t care A10/AP don‟t care A12/BC Selects burst chop mode on-the-fly, if enabled within MR0. A11, if available don't care Regular interface functionality during register reads Support two Burst Ordering which are switched with A2 and A[1:0]=00b. Support of read burst chop MRS and on-the-fly via A12/BC All other address bits remaining column address bits including A10, all bank address bits will be ignored by the DDR3 SDRAM. Regular read latencies and AC timings apply. DLL must be locked prior to MPR Reads. NOTE * Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Table MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] Function Burst Length BL8 Read Predefined Pattern for System Calibration Read Address A[2:0] Burst Order and Data Pattern 000b Burst order 0, 1, 2, 3, 4, 5, 6, 7 Pre-defined Data Pattern [0, 1, 0, 1, 0, 1, 0, 1] 000b Burst order 0, 1, 2, 3 Pre-defined Data Pattern [0, 1, 0, 1] 100b Burst order 4, 5, 6, 7 Pre-defined Data Pattern [0, 1, 0, 1] 000b Burst order 0, 1, 2, 3, 4, 5, 6, 7 000b Burst order 0, 1, 2, 3 100b Burst order 4, 5, 6, 7 000b Burst order 0, 1, 2, 3, 4, 5, 6, 7 000b Burst order 0, 1, 2, 3 100b Burst order 4, 5, 6, 7 000b Burst order 0, 1, 2, 3, 4, 5, 6, 7 000b Burst order 0, 1, 2, 3 100b Burst order 4, 5, 6, 7

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AS4C64M8D3-12BIN AS4C64M8D3-12BCN

Date Aug. 2017

Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice

Confidential
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AS4C64M8D3-12BIN AS4C64M8D3-12BCN
64M x 8 bit DDR3 Synchronous DRAM SDRAM
• JEDEC Standard Compliant
• Power supplies VDD & VDDQ = +1.5V 0.075V
• Operating temperature range:
- Commercial TC = 0~95°C - Industrial TC = -40~95°C
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate 800MHz
• Differential Clock, CK & CK#
• Bidirectional differential data strobe
- DQS & DQS#
• 8 internal banks for concurrent operation
• 8n-bit prefetch architecture
• Pipelined internal architecture
• Precharge & active power down
• Programmable Mode & Extended Mode
registers
• Additive Latency AL 0, CL-1, CL-2
• Programmable Burst lengths 4, 8
• Burst type Sequential / Interleave
• Output Driver Impedance Control
• 8192 refresh cycles / 64ms
- Average refresh period 7.8us -40°C +85°C 3.9us +85°C +95°C
• Write Leveling
• ZQ Calibration
• Dynamic ODT Rtt_Nom & Rtt_WR
• RoHS compliant
• Auto Refresh and Self Refresh
• 78-ball 8 x 1.0mm FBGA package - Pb and Halogen Free

Overview

The 512Mb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 512Mb chip is organized as 8Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.

The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks CK rising and CK# falling . All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ±0.075V power supply and are available in BGA packages.
Table Ordering Information

Product part No

Temperature

Max Clock MHz

AS4C64M8D3-12BCN 64M x 8 Commercial 0°C to 95°C

AS4C64M8D3-12BIN 64M x 8 Industrial -40°C to 95°C

Package 78-ball FBGA 78-ball FBGA

Table Speed Grade Information

Speed Grade

Clock Frequency CAS Latency

DDR3-1600
800 MHz
tRCD ns
tRP ns

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AS4C64M8D3-12BIN AS4C64M8D3-12BCN

Figure Ball Assignment FBGA Top View

TDQS#

VSSQ

TDQS

VDDQ

VSS VSSQ DQ3

VDD VDDQ VSSQ

VSSQ

DQS#

VSSQ

VREFDQ VDDQ

VDDQ

RAS#

CAS#

A10/AP

VREFCA

A12/BC#

VSS RESET#

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Figure Block Diagram

CK# CKE

DLL CLOCK BUFFER

RESET# CS#
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#

Table Burst Type and Burst Order

Burst Length

Read Write

Starting Column Address

A2 A1 A0

Sequential A3=0

Interleave A3=1

Note
0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T
0 1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T
0 1 0 2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T

Read
3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T
3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T
1, 2, 3

Chop
1 0 1 5, 6, 7, 4, T, T, T, T 5, 4, 7, 6, T, T, T, T
1 0 6, 7, 4, 5, T, T, T, T 6, 7, 4, 5, T, T, T, T
1 7, 4, 5, 6, T, T, T, T 7, 6, 5, 4, T, T, T, T

Write
0 V 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 1, 2, 4, 1 V 4, 5, 6, 7, X, X, X, X 4, 5, 6, 7, X, X, X, X 5
0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
0 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6
0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

Read
1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2
1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1
1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Write

V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2, 4

Note:

In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for
the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst
length being selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8
write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two
clocks.
0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.

T Output driver for data and strobes are in high impedance.

V a valid logic level 0 or 1 , but respective buffer input ignores level on input pins.
One bit wide logical interface via all DQ pins during READ operation. Register Read on x8 DQL[0] drive information from MPR. DQL[7:1] either drive the same information as DQL [0], or they drive 0b. Addressing during for Multi Purpose Register reads for all MPR agents BA [2:0] don‟t care A[1:0] A[1:0] must be equal to "00"b. Data read burst order in nibble is fixed A[2] For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], * For Burst Chop 4 cases, the burst order is switched on nibble base A [2]=0b, Burst order 0,1,2,3 * A[2]=1b, Burst order 4,5,6,7 * A[9:3] don‟t care A10/AP don‟t care A12/BC Selects burst chop mode on-the-fly, if enabled within MR0. A11, if available don't care Regular interface functionality during register reads Support two Burst Ordering which are switched with A2 and A[1:0]=00b. Support of read burst chop MRS and on-the-fly via A12/BC All other address bits remaining column address bits including A10, all bank address bits will be ignored by the DDR3 SDRAM. Regular read latencies and AC timings apply. DLL must be locked prior to MPR Reads. NOTE * Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.

Table MPR MR3 Register Definition

MR3 A[2]

MR3 A[1:0]

Function

Burst Length BL8

Read Predefined

Pattern for System

Calibration

Read Address A[2:0]

Burst Order and Data Pattern
000b

Burst order 0, 1, 2, 3, 4, 5, 6, 7

Pre-defined Data Pattern
[0, 1, 0, 1, 0, 1, 0, 1]
000b

Burst order 0, 1, 2, 3

Pre-defined Data Pattern
[0, 1, 0, 1]
100b

Burst order 4, 5, 6, 7

Pre-defined Data Pattern
[0, 1, 0, 1]
000b

Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3
100b

Burst order 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3
100b

Burst order 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3, 4, 5, 6, 7
000b

Burst order 0, 1, 2, 3
100b

Burst order 4, 5, 6, 7

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Datasheet ID: AS4C64M8D3-12BIN 516135