74ACTQ16543MTDX

74ACTQ16543MTDX Datasheet

74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs

Part	Datasheet
74ACTQ16543MTDX	74ACTQ16543MTDX (pdf)

Related Parts	Information
74ACTQ16543SSCX	74ACTQ16543SSCX
74ACTQ16543MTD	74ACTQ16543MTD
74ACTQ16543SSC	74ACTQ16543SSC

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74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs 74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs The ACTQ16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The ACTQ16543 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector for superior performance. s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Independent registers for A and B buses s Separate controls for data flow in each direction s Back-to-back registers for storage Multiplexed real-time and stored data transfers s Separate control logic for each byte s 16-bit version of the ACTQ543 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250pF loads Ordering Code: Order Number Package Number Package Description 74ACTQ16543SSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74ACTQ16543MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Descriptions OEABn OEBAn CEABn CEBAn LEABn LEBAn A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010967.prf 74ACTQ16543 Connection Diagram Pin Assignment for SSOP and TSSOP Functional Description The ACTQ16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-to-B Enable CEABn input must be LOW in order to enter data from or take data from as indicated in the Data I/O Control Table. With CEABn LOW, a LOW signal on the A-to-B Latch Enable LEABn input makes the A-to-B latches transparent a subsequent LOW-to-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBAn, LEBAn and OEBAn inputs. Data I/O Control Table CEABn H X L X L Inputs LEABn X H L X OEABn X H L Latch Status Byte n Latched Transparent Output Buffers Byte n High Z High Z Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn 74ACTQ16543 Logic Diagrams Byte 1 0:7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Byte 2 8:15 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACTQ16543 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin Storage Temperature −0.5V to +7.0V −20 mA +20 mA −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C

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74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs
74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs

The ACTQ16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow.

The ACTQ16543 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector for superior performance.
s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin output skew s Independent registers for A and B buses s Separate controls for data flow in each direction s Back-to-back registers for storage

Multiplexed real-time and stored data transfers s Separate control logic for each byte s 16-bit version of the ACTQ543 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250pF loads
Ordering Code:

Order Number Package Number

Package Description
74ACTQ16543SSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74ACTQ16543MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

Descriptions

OEABn OEBAn CEABn CEBAn LEABn LEBAn

A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs

B-to-A Data Inputs or A-to-B 3-STATE Outputs

FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010967.prf
74ACTQ16543

Connection Diagram

Pin Assignment for SSOP and TSSOP

Functional Description

The ACTQ16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-to-B Enable CEABn input must be LOW in order to enter data from or take data from as indicated in the Data I/O Control Table. With CEABn LOW, a LOW signal on the A-to-B Latch Enable LEABn input makes the A-to-B latches transparent a subsequent LOW-to-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBAn, LEBAn and OEBAn inputs.

Data I/O Control Table

CEABn H X L X L

Inputs

LEABn X H L X

OEABn X H L

Latch Status Byte n

Latched Transparent

Output Buffers Byte n High Z

High Z Driving

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown B-to-A flow control
is the same, except using CEBAn, LEBAn and OEBAn
74ACTQ16543

Logic Diagrams

Byte 1 0:7

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Byte 2 8:15

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACTQ16543

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin

Storage Temperature
−0.5V to +7.0V
−20 mA +20 mA
−20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA
±50 mA −65°C to +150°C

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Datasheet ID: 74ACTQ16543MTDX 513203