74F253SJX
74F253SJX Datasheet
74F253 Dual 4-Input Multiplexer with 3-STATE Outputs
| Part | Datasheet |
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74F253SJX |
74F253SJX (pdf) |
| Related Parts | Information |
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74F253PC |
74F253PC |
74F253SJ |
74F253SJ |
74F253SC |
74F253SC |
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74F253SCX |
74F253SCX |
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| 74F253 Dual 4-Input Multiplexer with 3-STATE Outputs 74F253 Dual 4-Input Multiplexer with 3-STATE Outputs The 74F253 is a dual 4-input multiplexer with 3-STATE outputs. It can select two bits of data from four sources using common select inputs. The output may be individually switched to a high impedance state with a HIGH on the respective Output Enable OE inputs, allowing the outputs to interface directly with bus oriented systems. s Multifunction capability s Non-inverting 3-STATE outputs Ordering Code: Order Number Package Number Package Description 74F253SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F253SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F253PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009505 74F253 Unit Loading/Fan Out Pin Names OEa OEb Za, Zb Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Output Enable Input Active LOW Side B Output Enable Input Active LOW 3-STATE Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Functional Description This device contains two identical 4-input multiplexers with 3-STATE outputs. They select two bits from four sources selected by common Select inputs S0, S1 . The 4-input multiplexers have individual Output Enable OEa, OEb inputs which, when HIGH, force the outputs to a high impedance High Z state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown below: Za = OEa • I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0 Zb = OEb • I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0 If the outputs of 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so that there is no overlap. Truth Table Select Inputs S0 S1 XX LL HL Data Inputs I0 I1 I2 I3 XXXX LXXX HXXX XLXX Output Enable OE H L Output Z L H L HL XHXX L HXX L X LHXXHX HHXXX L HHXXXH Address inputs S0 and S1 are common to both sections. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F253 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias |
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