74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs
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74ACT258SC (pdf) |
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74ACT258MTCX |
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74ACT258SCX |
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74ACT258SJX |
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74ACT258SJ |
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74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs 74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs April 2007 • ICC and IOZ reduced by 50% • Multiplexer expansion by tying outputs together • Inverting 3-STATE outputs • Outputs source/sink 24mA • TTL-compatible inputs The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement inverted form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable OE input, allowing the outputs to interface directly with bus-oriented systems. Ordering Information Order Number Package Number Package Description 74ACT258SC 74ACT258SJ 74ACT258MTC M16A M16D MTC16 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body 16-Lead Small Outline Package SOP , EIAJ TYPE 11, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Pin Description Pin Names S OE Description Common Data Select Input 3-STATE Output Enable Input Data Inputs from Source 0 Data Inputs from Source 1 3-STATE Inverting Data Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs Logic Symbol IEEE/IEC Functional Description The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a common Select input S . When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in inverted form. The ACT258 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Za = OE • I1a • S + I0a • S Zb = OE • I1b • S + I0b • S Zc = OE • I1c • S + I0c • S Zd = OE • I1d • S + I0d • S When the Output Enable input OE is HIGH, the outputs are forced to a high impedance state. If the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap. Truth Table Output Enable OE H L Select Input H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Data Inputs Outputs Z H L 1988 Fairchild Semiconductor Corporation 74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1988 Fairchild Semiconductor Corporation 74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C |
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