74ACT258PC

74ACT258PC Datasheet

74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs

Part	Datasheet
74ACT258PC	74ACT258PC (pdf)

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74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs 74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement inverted form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable OE input, allowing the outputs to interface directly with bus-oriented systems. s ICC and IOZ reduced by 50% s Multiplexer expansion by tying outputs together s Inverting 3-STATE outputs s Outputs source/sink 24 mA s TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT258SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body 74ACT258SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE 11, 5.3mm Wide 74ACT258MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT258PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names S OE Description Common Data Select Input 3-STATE Output Enable Input Data Inputs from Source 0 Data Inputs from Source 1 3-STATE Inverting Data Outputs is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS009950 74ACT258 Truth Table Output Enable OE H L Select Input H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Data Inputs Outputs Functional Description The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a common Select input S . When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in inverted form. The ACT258 is the logic implementation of a 4-pole, 2position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Za = OE • I1a • S + I0a • S Zb = OE • I1b • S + I0b • S Zc = OE • I1c • S + I0c • S Zd = OE • I1d • S + I0d • S When the Output Enable input OE is HIGH, the outputs are forced to a high impedance state. If the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACT258 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C 140°C Recommended Operating Conditions

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74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs
74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs

The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement inverted form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable OE input, allowing the outputs to interface directly with bus-oriented systems.
s ICC and IOZ reduced by 50% s Multiplexer expansion by tying outputs together s Inverting 3-STATE outputs s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACT258SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body
74ACT258SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE 11, 5.3mm Wide
74ACT258MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT258PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names S OE

Description Common Data Select Input 3-STATE Output Enable Input Data Inputs from Source 0 Data Inputs from Source 1 3-STATE Inverting Data Outputs
is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS009950
74ACT258

Truth Table

Output Enable

OE H L

Select Input

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Logic Diagram

Data

Inputs

Outputs

Functional Description

The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a common Select input S . When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in inverted form. The ACT258 is the logic implementation of a 4-pole, 2position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below:

Za = OE
• I1a
• S + I0a
• S

Zb = OE
• I1b
• S + I0b
• S

Zc = OE
• I1c
• S + I0c
• S

Zd = OE
• I1d
• S + I0d
• S

When the Output Enable input OE is HIGH, the outputs are forced to a high impedance state. If the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACT258

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

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Datasheet ID: 74ACT258PC 513169