74AC648SCX

74AC648SCX Datasheet

74AC648 Octal Transceiver/Register with 3-STATE Outputs

Part	Datasheet
74AC648SCX	74AC648SCX (pdf)

Related Parts	Information
74AC648SPC	74AC648SPC
74AC648SC	74AC648SC

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74AC648 Octal Transceiver/Register with 3-STATE Outputs 74AC648 Octal Transceiver/Register with 3-STATE Outputs The AC648 consists of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin CPAB or CPBA . The four fundamental data handling functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil slim dual-in-line package s Outputs source/sink 24 mA s Inverted data to output Ordering Code: Order Number Package Number Package Description 74AC648SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74AC648SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names CPAB, CPBA SAB, SBA DIR, G Data Register A Inputs, Data Register A 3-STATE Outputs Data Register B Inputs, Data Register B 3-STATE Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Inputs is a trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010133 74AC648 Function Table Inputs Data I/O Note 1 Function G DIR CPAB CPBA SAB SBA X H or L H or L X Isolation Input Clock An Data into A Register Clock Bn Data into B Register An to Time Transparent Mode Input Output Clock An Data into A Register H or L X A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn Bn to An Time Transparent Mode L Output Input Clock Bn Data into B Register X H or L X B Register to An Stored Mode Clock Bn Data into B Register and Output to An H = HIGH Voltage Level L = LOW Voltage Level = Irrelevant = LOW-to-HIGH Transition Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. Real Time Transfer A-Bus to B-Bus Real Time Transfer B-Bus to A-Bus FIGURE Storage from Bus to Register FIGURE Transfer from Register to Bus FIGURE FIGURE 74AC648 Logic Diagram

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74AC648 Octal Transceiver/Register with 3-STATE Outputs
74AC648 Octal Transceiver/Register with 3-STATE Outputs

The AC648 consists of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin CPAB or CPBA . The four fundamental data handling functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure
s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil slim dual-in-line package s Outputs source/sink 24 mA s Inverted data to output
Ordering Code:

Order Number Package Number

Package Description
74AC648SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74AC648SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

CPAB, CPBA SAB, SBA DIR, G

Data Register A Inputs, Data Register A 3-STATE Outputs Data Register B Inputs, Data Register B 3-STATE Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Inputs
is a trademark of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010133
74AC648

Function Table

Inputs

Data I/O Note 1

Function

G DIR CPAB CPBA SAB SBA

X H or L H or L X

Isolation

Input Clock An Data into A Register

Clock Bn Data into B Register

An to Time Transparent Mode

Input Output Clock An Data into A Register

H or L X

A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn

Bn to An Time Transparent Mode

L Output Input Clock Bn Data into B Register

X H or L X

B Register to An Stored Mode Clock Bn Data into B Register and Output to An

H = HIGH Voltage Level L = LOW Voltage Level
= Irrelevant = LOW-to-HIGH Transition

Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.

Real Time Transfer A-Bus to B-Bus

Real Time Transfer B-Bus to A-Bus

FIGURE

Storage from Bus to Register

FIGURE

Transfer from Register to Bus

FIGURE

FIGURE
74AC648

Logic Diagram

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Datasheet ID: 74AC648SCX 513108