4162135-XX

4162135-XX Datasheet

LVDS Add On Board P/N 4162135-11

Part	Datasheet
4162135-XX	4162135-XX (pdf)

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LVDS Add On Board P/N 4162135-11 The LVDS add-on board P/N 4162135-11 design for dual pixel LVDS panels. It provides jumper setting to select the Data Enable DE signal on transmitter chips. Jumper Settings JP1- Clock phase selection Default 2-3 closed Change this setting to obtain best quality. JP2 - Panel voltage selection 1-3, 2-4 closed 12V panel 3-5, 4-6 closed / 5V panel Default JP3 Enable DE signal on signal or dual LVDS transmitter chip at even pixel side 1-2 closed Enable DE signal on both LVDS transmitter chips U1 & U2 Default - Use for all panels 2-3 closed Enable DE signal on single LVDS transmitter chip U1 Use for all panel except NEC NL128102AC28-04 and NEC NL128102AC31-02A Compatible with LVDS board : Old LVDS board Jumper setting on LVDS board P/N 4162135-11 P/N 4162135-10 JP1 2-3 closed JP2 1-3, 2-4 closed JP3 1-2 closed P/N 4162147-00 JP1 2-3 closed JP2 3-5, 4-6 closed JP3 1-2 closed Use of connectors Connector CN2 CN3 CN4 CN5 CN6 Connector type Hirose DF11-28DS-2DSA Hirose DF11-32DS-2DSA Hirose DF11-20DF-2DSA Hirose DF14-20P-1.25P Hirose DF14-25P-1.25P Mechanical Drawing : Pin Assignments : CN5 - Hirose DF14-20P-1.25P PIN SYMBOL No connection Ground OUTO3 Positive differential LVDS data O3 /OUTO3 Negative differential LVDS data O3 Ground CLKOUTO Positive LVDS clock O /CLKOUTO Negative LVDS clock O Ground OUTO2 Positive differential LVDS data O2 /OUTO2 Negative differential LVDS data O2 Ground OUTO1 Positive differential LVDS data O1 /OUTO1 Negative differential LVDS data O1 Ground OUTO0

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LVDS Add On Board P/N 4162135-11

The LVDS add-on board P/N 4162135-11 design for dual pixel LVDS panels. It provides jumper setting to select the Data Enable DE signal on transmitter chips.

Jumper Settings JP1- Clock phase selection Default 2-3 closed

Change this setting to obtain best quality.

JP2 - Panel voltage selection 1-3, 2-4 closed 12V panel 3-5, 4-6 closed / 5V panel Default

JP3 Enable DE signal on signal or dual LVDS transmitter chip at even pixel side 1-2 closed Enable DE signal on both LVDS transmitter chips U1 & U2 Default - Use for all panels
2-3 closed Enable DE signal on single LVDS transmitter chip U1 Use for all panel except NEC NL128102AC28-04 and NEC NL128102AC31-02A

Compatible with LVDS board :

Old LVDS board

Jumper setting on LVDS board P/N 4162135-11

P/N 4162135-10 JP1 2-3 closed JP2 1-3, 2-4 closed JP3 1-2 closed

P/N 4162147-00 JP1 2-3 closed JP2 3-5, 4-6 closed JP3 1-2 closed

Use of connectors Connector CN2 CN3 CN4 CN5 CN6

Connector type Hirose DF11-28DS-2DSA Hirose DF11-32DS-2DSA Hirose DF11-20DF-2DSA Hirose DF14-20P-1.25P Hirose DF14-25P-1.25P

Mechanical Drawing :

Pin Assignments :

CN5 - Hirose DF14-20P-1.25P

PIN SYMBOL

No connection

Ground

OUTO3

Positive differential LVDS data O3
/OUTO3

Negative differential LVDS data O3

Ground

CLKOUTO

Positive LVDS clock O
/CLKOUTO

Negative LVDS clock O

Ground

OUTO2

Positive differential LVDS data O2
/OUTO2

Negative differential LVDS data O2

Ground

OUTO1

Positive differential LVDS data O1
/OUTO1

Negative differential LVDS data O1

Ground

OUTO0

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Datasheet ID: 4162135-XX 509773