LD16ZC224KAB2A

LD16ZC224KAB2A Datasheet


LD18

Part Datasheet
LD16ZC224KAB2A LD16ZC224KAB2A LD16ZC224KAB2A (pdf)
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Low Inductance Capacitors

Introduction

The signal integrity characteristics of a Power Delivery Network PDN are becoming critical aspects of board level and semiconductor package designs due to higher operating frequencies, larger power demands, and the ever shrinking lower and upper voltage limits around low operating voltages. These power system challenges are coming from mainstream designs with operating frequencies of 300MHz or greater, modest ICs with power demand of 15 watts or more, and operating voltages below 3 volts.

The classic PDN topology is comprised of a series of capacitor stages. Figure 1 is an example of this architecture with multiple capacitor stages.

An ideal capacitor can transfer all its stored energy to a load instantly. A real capacitor has parasitics that prevent instantaneous transfer of a capacitor’s stored energy. The true nature of a capacitor can be modeled as an RLC equivalent circuit. For most simulation purposes, it is possible to model the characteristics of a real capacitor with one
capacitor, one resistor, and one inductor. The RLC values in this model are commonly referred to as equivalent series capacitance ESC , equivalent series resistance ESR , and equivalent series inductance ESL .

The ESL of a capacitor determines the speed of energy transfer to a load. The lower the ESL of a capacitor, the faster that energy can be transferred to a load. Historically, there has been a tradeoff between energy storage capacitance and inductance speed of energy delivery . Low ESL devices typically have low capacitance. Likewise, higher capacitance devices typically have higher ESLs. This tradeoff between ESL speed of energy delivery and capacitance energy storage drives the PDN design topology that places the fastest low ESL capacitors as close to the load as possible. Low Inductance MLCCs are found on semiconductor packages and on boards as close as possible to the load.

Slowest Capacitors

Fastest Capacitors

Semiconductor Product

Bulk

Board-Level

Package-Level Die-Level

Low Inductance Decoupling Capacitors Figure 1 Classic Power Delivery Network PDN Architecture

LOW INDUCTANCE CHIP CAPACITORS

When the distance between terminations is reduced, the size of the current loop is reduced. Since the size of the current loop is the primary driver of inductance, an 0306 with a smaller current loop has significantly lower ESL then an The reduction in ESL varies by EIA size, however, ESL is typically reduced 60% or more with an LICC versus a standard MLCC.

INTERDIGITATED CAPACITORS

The size of a current loop has the greatest impact on the ESL characteristics of a surface mount capacitor. There is a secondary method for decreasing the ESL of a capacitor. This secondary method uses adjacent opposing current loops to reduce ESL. The InterDigitated Capacitor IDC utilizes both primary and secondary methods of reducing inductance. The IDC architecture shrinks the distance between terminations to minimize the current loop size, then further reduces inductance by creating adjacent opposing current loops.

An IDC is one single capacitor with an internal structure that has been optimized for low ESL. Similar to standard MLCC versus LICCs, the reduction in ESL varies by EIA case size. Typically, for the same EIA size, an IDC delivers an ESL that is at least 80% lower than an MLCC.

Low Inductance Capacitors

Introduction

LAND GRID ARRAY LGA CAPACITORS

Land Grid Array LGA capacitors are based on the first Low ESL MLCC technology created to specifically address the design needs of current day Power Delivery Networks PDNs . This is the 3rd low inductance capacitor technology developed by AVX. LGA technology provides engineers with new options. The LGA internal structure and manufacturing technology eliminates the historic need for a device to be physically small to create small current loops to minimize inductance.

The first family of LGA products are 2 terminal devices. A 2 terminal 0306 LGA delivers ESL performance that is equal to or better than an 0306 8 terminal IDC. The 2 terminal 0805 LGA delivers ESL performance that approaches the 0508 8 terminal IDC. New designs that would have used 8 terminal IDCs are moving to 2 terminal LGAs because the layout is easier for a 2 terminal device and manufacturing yield is better for a 2 terminal LGA versus an 8 terminal IDC.

LGA technology is also used in a 4 terminal family of products that AVX is sampling and will formerly introduce in Beyond 2008, there are new multi-terminal LGA product families that will provide even more attractive options for PDN designers.

LOW INDUCTANCE CHIP ARRAYS

The product family is the result of a joint development effort between AVX and IBM to develop a high performance MLCC family of decoupling capacitors. LICA was introduced in the 1980s and remains the leading choice of designers in high performance semiconductor packages and high reliability board level decoupling applications.
products are used in uptime semiconductor package applications on both ceramic and organic substrates. The C4 solder ball termination option is the perfect compliment to flip-chip packaging technology. Mainframe class CPUs, ultimate performance multi-chip modules, and communications systems that must have the reliability of 5 9’s use
products with either Sn/Pb or Pb-free solder balls are used for decoupling in high reliability military and aerospace applications. These devices are used for decoupling of large pin count FPGAs, ASICs, CPUs, and other high power ICs with low operating voltages.

When high reliability decoupling applications require the very lowest ESL capacitors, products are the best option.
470 nF 0306 Impedance Comparison
0306 2T-LGA 0306 LICC 0306 8T-IDC 0603 MLCC

Impedance ohms

Frequency MHz
1000

Figure 2 MLCC, LICC, IDC, and LGA technologies deliver different levels of equivalent series inductance ESL .

Low Inductance Capacitors SnPb
0612/0508/0306/0204 Tin Lead Termination “B”

The key physical characteristic determining equivalent series inductance ESL of a capacitor is the size of the current loop it creates. The smaller the current loop, the lower the ESL.

When the distance between terminations is reduced, the size of the current loop is reduced. Since the size of the current loop is the primary driver of inductance, an 0306 with a smaller current loop has significantly lower ESL then an The reduction in ESL varies by EIA size, however, ESL is typically reduced 60% or more with an LICC versus a standard MLCC.

AVX LICC products are available with a lead termination for high reliability military and aerospace applications that must avoid tin whisker reliability issues.
More datasheets: LD18ZC225KAB2A | LD17YC563KAB2S | LD17YC563KAB2A | LD16ZC104KAB2A | LD18YC105KAB2A | LD18YD105KAB2A | LD17YC153KAB2S | LD17YC222KAB2A | LD17YC222KAB2S | LD17YC153KAB2A


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Datasheet ID: LD16ZC224KAB2A 521420