74ACT377SJ
74ACT377SJ Datasheet
74AC377<br>• 74ACT377 Octal D-Type Flip-Flop with Clock Enable
| Part | Datasheet |
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74ACT377SJ |
74ACT377SJ (pdf) |
| Related Parts | Information |
|---|---|
74ACT377SJX |
74ACT377SJX |
74ACT377PC |
74ACT377PC |
74ACT377MTC |
74ACT377MTC |
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74ACT377SCX |
74ACT377SCX |
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74ACT377SC |
74ACT377SC |
74ACT377MTCX |
74ACT377MTCX |
| PDF Datasheet Preview |
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| 74AC377 • 74ACT377 Octal D-Type Flip-Flop with Clock Enable 74AC377 • 74ACT377 Octal D-Type Flip-Flop with Clock Enable The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable CE is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. s ICC reduced by 50% s Ideal for addressable register applications s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s Outputs source/sink 24 mA s See 273 for master reset version s See 373 for transparent latch version s See 374 for 3-STATE version s ACT377 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC377SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74AC377SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74AC377MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74AC377PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT377SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACT377SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACT377MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT377PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CE CP Description Data Inputs Clock Enable Active LOW Data Outputs Clock Pulse Input is a trademark of Fairchild Semiconductor Corporation. 2001 Fairchild Semiconductor Corporation DS009961 74AC377 • 74ACT377 Logic Symbols IEEE/IEC Mode Select-Function Table Operating Mode Load ‘1' Load ‘0' Hold Do Nothing H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Clock Transition Logic Diagram Inputs Outputs X No Change X No Change Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC377 • 74ACT377 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C 140°C Recommended Operating Conditions Supply Voltage VCC AC 2.0V to 6.0V 4.5V to 5.5V Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C AC Devices |
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