CS61583-IQ5ZR

CS61583-IQ5ZR Datasheet

CS61583

Part	Datasheet
CS61583-IQ5ZR	CS61583-IQ5ZR (pdf)

Related Parts	Information
CS61583-IQ5Z	CS61583-IQ5Z

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CS61583 Dual T1/E1 Line Interface • Dual T1/E1 Line Interface • Low Power Consumption Typically 220mW per Line Interface • Matched Impedance Transmit Drivers • Common Transmit and Receive Transform- ers for all Modes • Selectable Jitter Attenuation for Transmit or Receive Paths • Supports JTAG Boundary Scan • Hardware Mode Derivative of the CS61584 The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. Each channel features individual control and status pins which eliminates the need for external microprocessor support. The matched impedance drivers reduce power consumption and provide substantial return loss to insure superior T1/E1 pulse quality. The CS61583 provides JTAG boundary scan to enhance system testability and reliability. The CS61583 is a 5 volt device and is a hardware mode derivative of the CS61584. ORDERING INFORMATION CS61583-IL5 68-pin PLCC, -40 to +85 °C CS61583-IQ5 64-pin TQFP, -40 to +85 °C CLKE ATTEN2 AMI1 CON11 TAOS1 RLOOP1 AMI2 CON12 TAOS2 RLOOP2 RESET ATTEN1 CODER1 CON01 CON21 LLOOP1 CODER2 CON02 CON22 LLOOP2 TCLK1 TPOS1/ TDATA1 TNEG1/ AIS1 RCLK1 RPOS1/ RDATA1 RNEG1/ BPV1 TCLK2 TPOS2/ TDATA2 TNEG2/ AIS2 RCLK2 RPOS2/ RDATA2 RNEG2/ BPV2 JITTER ATTENUATOR JITTER ATTENUATOR CONTROL TAOS DETECT PULSE SHAPING CIRCUITRY CLOCK & DATA RECOVERY TAOS DETECT PULSE SHAPING CIRCUITRY CLOCK & DATA RECOVERY DRIVER RECEIVER DRIVER RECEIVER TTIP1 TRING1 Boundary Scan Register The BSR is connected in parallel to all the digital I/O pins, and provides the mechanism for applying/reading test patterns to/from the board traces. The BSR is 67 bits long and is initialized and read using the instruction SAMPLE/PRELOAD. The bit ordering for the BSR is the same as the top-view package pin out, beginning with the LOS1 pin and moving counter-clockwise to end with the CODER1 pin as shown in Table Note that the analog, oscillator, power, ground, CLKE, and ATTEN0 pins are not included as part of the boundaryscan register. The input pins require one bit in the BSR and only one J-TCK cycle is required to load test data for each input pin. The output pins have two bits in the BSR to define output high, output low, or high impedance. Digital output pins Digital input pins J-TDI J-TCK J-TMS parallel latched output Boundary Scan Data Register Device ID Data Register Bypass Data Register Instruction shift Register parallel latched output TAP Controller JTAG Block MUX J-TDO Figure Block Diagram of JTAG Circuitry DS172PP5 CS61583 The first bit shifted in first selects between an output-enabled state bit set to 1 or high-impedance state bit set to The second bit shifted in contains the test data that may be output on the pin. Therefore, two J-TCK cycles are required to load test data for each output pin. BSR bits 0-2 3-5 6 7 8-9 10-11 12-13 14-16 17-19 20 21-23 24-26 27-29 30-32 33-35 36-38 39-41 42-44 45 46-48 49-50 51-52 53-54 55 56 57-59 60-62 63 64 65 66 Pin Name LOS1 TNEG1/AIS1 TPOS1/TDATA1 TCLK1 RNEG1/BPV1 RPOS1/RDATA1 RCLK1 ATTEN1 RLOOP1 LLOOP1 LLOOP2 TAOS1 TAOS2 CON01 CON02 CON11 CON12 CON21 CON22 AMI1 RCLK2 RPOS2/RDATA2 RNEG2/BPV2 TCLK2 TPOS2/TDATA2 TNEG2/AIS2 LOS2 AMI2 CODER2 RLOOP2 CODER1 Pad Type bi-directional2 bi-directional input input output output output bi-directional1 bi-directional1 input bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 input bi-directional1 output output output input input ORDERING INFORMATION CDB61583 +5V 0V TCLK1 TPOS1 TDATA1 TNEG1 CHANNEL 1 RCLK1 RPOS1 RDATA1 RNEG1 BPV1 RESET CIRCUIT Hardware Control and Mode Circuit LED Status Indicators CS61583 TCLK2 TPOS2 TDATA2 TNEG2 CHANNEL 2 RCLK2 RPOS2 RDATA2 RNEG2 BPV2 TRING1 RTIP1 CHANNEL 1 RRING1 REFCLK Oscillator Circuit TRING2 RTIP2 CHANNEL 2 RRING2 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 512 445-7222 FAX 512 445 7581 Copyright Crystal Semiconductor Corporation 1995 All Rights Reserved DEC ’95 DB172PP1 CDB61583 POWER SUPPLY Capacitors C3, C5-C8, C13, C18, and C38 provide power supply decoupling for the CS61583. The BGREF pin is pulled down through resistor R10 to provide an internal current reference. The buffers are decoupled using capacitors C9, C15, and C19. Ferrite beads L2-L4 help reduce the power supply noise that is coupled from the buffers to the power supply. BOARD CONFIGURATION The evaluation board is based on the CDB61584 used to evaluate the CS61584 dual LIU optimized for Host mode applications. Because the CS61583 is optimized for Hardware mode applications, slide switch SW6 must be placed in the "HW" position to set the AGND1 pin of the CS61583 to a logic In addition, the host processor interface appearing at J26 is not used on the CDB61583. The evaluation board is configured using DIP switches SW2, SW3, and SW4. Because the evaluation board is based on the CDB61584 design, switches SW2, SW3, and SW4 are relabeled with white stickers. These switches establish the digital control inputs for both line interface channels. Closing a DIP switch towards the label sets the CS61583 control pin of the same name to a logic All switch inputs are pulled-down using resistor networks RP2-RP5. The CDB61583 switch functions are listed below: • TAOS1, TAOS2 transmit all ones; • LLOOP1, LLOOP2 local loopback;

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CS61583

Dual T1/E1 Line Interface
• Dual T1/E1 Line Interface
• Low Power Consumption

Typically 220mW per Line Interface
• Matched Impedance Transmit Drivers
• Common Transmit and Receive Transform-
ers for all Modes
• Selectable Jitter Attenuation for Transmit
or Receive Paths
• Supports JTAG Boundary Scan
• Hardware Mode Derivative of the CS61584

The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. Each channel features individual control and status pins which eliminates the need for external microprocessor support. The matched impedance drivers reduce power consumption and provide substantial return loss to insure superior T1/E1 pulse quality.

The CS61583 provides JTAG boundary scan to enhance system testability and reliability. The CS61583 is a 5 volt device and is a hardware mode derivative of the CS61584.
ORDERING INFORMATION CS61583-IL5 68-pin PLCC, -40 to +85 °C CS61583-IQ5 64-pin TQFP, -40 to +85 °C

CLKE

ATTEN2

AMI1

CON11

TAOS1

RLOOP1

AMI2

CON12

TAOS2

RLOOP2

RESET

ATTEN1

CODER1 CON01

CON21

LLOOP1

CODER2 CON02

CON22

LLOOP2

TCLK1

TPOS1/ TDATA1 TNEG1/ AIS1

RCLK1

RPOS1/ RDATA1 RNEG1/ BPV1

TCLK2 TPOS2/ TDATA2 TNEG2/ AIS2

RCLK2 RPOS2/ RDATA2 RNEG2/ BPV2

JITTER ATTENUATOR

JITTER ATTENUATOR

CONTROL

TAOS

DETECT

PULSE SHAPING CIRCUITRY

CLOCK & DATA

RECOVERY

TAOS

DETECT

PULSE SHAPING CIRCUITRY

CLOCK & DATA

RECOVERY

DRIVER RECEIVER

DRIVER RECEIVER

TTIP1 TRING1
Boundary Scan Register The BSR is connected in parallel to all the digital I/O pins, and provides the mechanism for applying/reading test patterns to/from the board traces. The BSR is 67 bits long and is initialized and read using the instruction SAMPLE/PRELOAD. The bit ordering for the BSR is the same as the top-view package pin out, beginning with the LOS1 pin and moving counter-clockwise to end with the CODER1 pin as shown in Table Note that the analog, oscillator, power, ground, CLKE, and ATTEN0 pins are not included as part of the boundaryscan register.

The input pins require one bit in the BSR and only one J-TCK cycle is required to load test data for each input pin.

The output pins have two bits in the BSR to define output high, output low, or high impedance.

Digital output pins Digital input pins

J-TDI J-TCK J-TMS
parallel latched output

Boundary Scan Data Register

Device ID Data Register

Bypass Data Register

Instruction shift Register parallel latched
output TAP Controller

JTAG Block MUX

J-TDO

Figure Block Diagram of JTAG Circuitry

DS172PP5

CS61583

The first bit shifted in first selects between an output-enabled state bit set to 1 or high-impedance state bit set to The second bit shifted in contains the test data that may be output on the pin. Therefore, two J-TCK cycles are required to load test data for each output pin.

BSR bits 0-2 3-5 6 7 8-9
10-11 12-13 14-16 17-19
20 21-23 24-26 27-29 30-32 33-35 36-38 39-41 42-44
45 46-48 49-50 51-52 53-54
55 56 57-59 60-62 63 64 65 66

Pin Name LOS1

TNEG1/AIS1 TPOS1/TDATA1

TCLK1 RNEG1/BPV1 RPOS1/RDATA1

RCLK1 ATTEN1 RLOOP1 LLOOP1 LLOOP2 TAOS1 TAOS2 CON01 CON02 CON11 CON12 CON21 CON22

AMI1 RCLK2 RPOS2/RDATA2 RNEG2/BPV2 TCLK2 TPOS2/TDATA2 TNEG2/AIS2 LOS2 AMI2 CODER2 RLOOP2 CODER1

Pad Type bi-directional2
bi-directional
input
input
output
output
output bi-directional1 bi-directional1
input bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1 bi-directional1
input bi-directional1
output
output
output
input
input
ORDERING INFORMATION CDB61583
+5V 0V

TCLK1

TPOS1 TDATA1

TNEG1

CHANNEL 1

RCLK1

RPOS1

RDATA1

RNEG1 BPV1

RESET

CIRCUIT

Hardware Control and Mode Circuit

LED Status Indicators

CS61583

TCLK2

TPOS2 TDATA2

TNEG2

CHANNEL 2

RCLK2

RPOS2 RDATA2

RNEG2 BPV2

TRING1 RTIP1

CHANNEL 1

RRING1 REFCLK

Oscillator Circuit

TRING2 RTIP2

CHANNEL 2

RRING2

Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 512 445-7222 FAX 512 445 7581

Copyright Crystal Semiconductor Corporation 1995 All Rights Reserved

DEC ’95 DB172PP1

CDB61583

POWER SUPPLY

Capacitors C3, C5-C8, C13, C18, and C38 provide power supply decoupling for the CS61583. The BGREF pin is pulled down through resistor R10 to provide an internal current reference. The buffers are decoupled using capacitors C9, C15, and C19. Ferrite beads L2-L4 help reduce the power supply noise that is coupled from the buffers to the power supply.

BOARD CONFIGURATION

The evaluation board is based on the CDB61584 used to evaluate the CS61584 dual LIU optimized for Host mode applications. Because the CS61583 is optimized for Hardware mode applications, slide switch SW6 must be placed in the "HW" position to set the AGND1 pin of the CS61583 to a logic In addition, the host processor interface appearing at J26 is not used on the CDB61583.

The evaluation board is configured using DIP switches SW2, SW3, and SW4. Because the evaluation board is based on the CDB61584 design, switches SW2, SW3, and SW4 are relabeled with white stickers. These switches establish the digital control inputs for both line interface channels. Closing a DIP switch towards the label sets the CS61583 control pin of the same name to a logic All switch inputs are pulled-down using resistor networks RP2-RP5.

The CDB61583 switch functions are listed below:
• TAOS1, TAOS2 transmit all ones;
• LLOOP1, LLOOP2 local loopback;

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CS61583-IQ5ZR Datasheet file may be downloaded here without warranties.

Datasheet ID: CS61583-IQ5ZR 523207