74ABT16646CMTD
74ABT16646CMTD Datasheet
74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs
| Part | Datasheet |
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74ABT16646CMTD |
74ABT16646CMTD (pdf) |
| Related Parts | Information |
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74ABT16646CMTDX |
74ABT16646CMTDX |
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74ABT16646CSSC |
74ABT16646CSSC |
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74ABT16646CSSCX |
74ABT16646CSSCX |
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| 74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs 74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs The ABT16646 consists of bus transceiver circuits with 3STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time transparent mode data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode control OE HIGH , A data may be stored in the B register and/or B data may be stored in the A register. s Independent registers for A and B buses s Multiplexed real-time and stored data s A and B output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number Package Number Package Description 74ABT16646CSSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names CPABn, CPBAn SABn, SBAn OEn DIR Description Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input 1999 Fairchild Semiconductor Corporation DS011644 74ABT16646 Function Table Inputs Data I/O Note 1 Output Operation Mode OE1 DIR1 CPAB1 CPBA1 SAB1 SBA1 X H or L H or L X Input Input Isolation Clock An Data into A Register Clock Bn Data Into B Register An to Time Transparent Mode Input Output Clock An Data to A Register H or L X A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn Bn to Time Transparent Mode L Output Input Clock Bn Data into B Register X H or L X B Register to An Stored Mode Clock Bn into B Register and Output to An H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition Note 1 The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O A and B 8-15 and #2 control pins. Real Time Transfer A-Bus to B-Bus Real Time Transfer B-Bus to A-Bus FIGURE Storage from Bus to Register FIGURE Transfer from Register to Bus FIGURE FIGURE 74ABT16646 Logic Diagram 74ABT16646 Absolute Maximum Ratings Note 2 |
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