74ABT16543CSSCX

74ABT16543CSSCX Datasheet

74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs

Part	Datasheet
74ABT16543CSSCX	74ABT16543CSSCX (pdf)

Related Parts	Information
74ABT16543CMTDX	74ABT16543CMTDX
74ABT16543CSSC	74ABT16543CSSC
74ABT16543CMTD	74ABT16543CMTD

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74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs 74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs The ABT16543 16-bit transceiver contains two sets of Dtype latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation. s Back-to-back registers for storage s Bidirectional data path s A and B outputs have current sourcing capability of 32 mA and current sinking capability of 64 mA s Separate control logic for each byte s 16-bit version of the ABT543 s Separate controls for data flow in each direction s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number Package Number Package Description 74ABT16543CSSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74ABT16543CMTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names OEABn OEBAn CEABn CEBAn LEABn LEBAn A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs 1999 Fairchild Semiconductor Corporation DS011646.prf 74ABT16543 Logic Symbol Data I/O Control Table Inputs Latch Status Output Buffers CEABn LEABn OEABn Byte n Byte n Latched HIGH Z Latched X Transparent HIGH Z Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn Functional Description The ABT16543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable CEAB input must be low in order to enter data from the A port or take data from the B-Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on LEAB input makes the A to B latches transparent a subsequent low to high transition of the LEAB line puts the A latches in the storage Logic Diagrams mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate control inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver. Byte 1 0:7 Byte 2 8:15 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ABT16543 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin

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74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs
74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs

The ABT16543 16-bit transceiver contains two sets of Dtype latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation.
s Back-to-back registers for storage s Bidirectional data path s A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA s Separate control logic for each byte s 16-bit version of the ABT543 s Separate controls for data flow in each direction s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:

Order Number Package Number

Package Description
74ABT16543CSSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74ABT16543CMTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Assignment for SSOP and TSSOP

Pin Names

OEABn OEBAn CEABn CEBAn LEABn LEBAn

A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs

B-to-A Data Inputs or A-to-B 3-STATE Outputs
1999 Fairchild Semiconductor Corporation DS011646.prf
74ABT16543

Logic Symbol

Data I/O Control Table

Inputs

Latch Status Output Buffers

CEABn LEABn OEABn Byte n

Byte n

Latched

HIGH Z

Latched

X Transparent

HIGH Z

Driving

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown;

B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn

Functional Description

The ABT16543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable CEAB input must be low in order to enter data from the A port or take data from the B-Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on LEAB input makes the A to B latches transparent a subsequent low to high transition of the LEAB line puts the A latches in the storage

Logic Diagrams
mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate control inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver.

Byte 1 0:7

Byte 2 8:15

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ABT16543

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin

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Datasheet ID: 74ABT16543CSSCX 513040