74ABT16374CMTDX
74ABT16374CMTDX Datasheet
74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
| Part | Datasheet |
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74ABT16374CMTDX |
74ABT16374CMTDX (pdf) |
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74ABT16374CMTD |
74ABT16374CMTD |
74ABT16374CSSCX |
74ABT16374CSSCX |
74ABT16374CSSC |
74ABT16374CSSC |
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| 74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs 74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs The ABT16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and Output Enable OE are common to each byte and can be shorted together for full 16-bit operation. s Separate control logic for each byte s 16-bit version of the ABT374 s Edge-triggered D-type inputs s Buffered Positive edge-triggered clock s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Guaranteed latch-up protection Ordering Code: Order Number Package Number Package Description 74ABT16374CSSC MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74ABT16374CMTD MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Name OEn CPn 3-STATE Output Enable Input Active LOW Clock Pulse Input Active Rising Edge Data Inputs 3-STATE Outputs 2005 Fairchild Semiconductor Corporation DS011668 74ABT16374 Functional Description The ABT16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Logic Diagrams Truth Tables Inputs OE1 L Inputs OE2 L H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Byte 1 0:7 Outputs H L Previous Z Outputs H L Previous Z Byte 2 8:15 74ABT16374 Absolute Maximum Ratings Note 1 Recommended Operating Storage Temperature to Conditions Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output in the Disabled or to mA to mA Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate 'V/'t Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100mV/ns Power-Off State to 5.5V in the HIGH State Current Applied to Output to VCC in LOW State Max DC Latchup Source Current: twice the rated IOL mA |
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