100351QIX

100351QIX Datasheet

100351 Low Power Hex D-Type Flip-Flop

Part	Datasheet
100351QIX	100351QIX (pdf)

Related Parts	Information
100351QC	100351QC
100351QCX	100351QCX
100351QI	100351QI
100351SC	100351SC
100351SCX	100351SCX

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100351 Low Power Hex D-Type Flip-Flop 100351 Low Power Hex D-Type Flip-Flop The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs CPa and CPb and common Master Reset MR input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb or both go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 pull-down resistors. s 40% power reduction of the 100151 s 2000V ESD protection s Pin/function compatible with 100151 s Voltage compensated operating range: −4.2V to −5.7V s Available to industrial grade temperature range Ordering Code: Order Number Package Number Package Description 100351SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 100351PC N24E 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-010, Wide 100351QC V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square 100351QI V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Industrial Temperature Range −40°C to +85°C Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC Pin Descriptions Pin Names CPa, CPb MR Description Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs 2000 Fairchild Semiconductor Corporation DS009885 28-Pin PLCC 100351 Truth Tables Each Flip-flop Synchronous Operation Inputs Dn L H L H X H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care t = Time before CP positive transition = Time after CP positive transition = LOW-to-HIGH transition Outputs Qn t+1 L H L H Qn t Qn t Qn t Logic Diagram Asynchronous Operation Inputs Outputs Qn t+1 100351 Absolute Maximum Ratings Note 1 Storage Temperature TSTG Maximum Junction Temperature TJ VEE Pin Potential to Ground Pin Input Voltage DC Output Current DC Output HIGH ESD Note 2 −65°C to +150°C +150°C −7.0V to +0.5V VEE to +0.5V −50 mA Recommended Operating Conditions Case Temperature TC Commercial 0°C to +85°C Industrial −40°C to +85°C Supply Voltage VEE −5.7V to −4.2V Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions

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100351 Low Power Hex D-Type Flip-Flop
100351 Low Power Hex D-Type Flip-Flop

The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs CPa and CPb and common Master Reset MR input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb or both go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 pull-down resistors.
s 40% power reduction of the 100151 s 2000V ESD protection s Pin/function compatible with 100151 s Voltage compensated operating range:
−4.2V to −5.7V s Available to industrial grade temperature range
Ordering Code:

Order Number Package Number

Package Description
100351SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
100351PC

N24E
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-010, Wide
100351QC

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square
100351QI

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Industrial Temperature Range −40°C to +85°C
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagrams
24-Pin DIP/SOIC

Pin Descriptions

Pin Names CPa, CPb MR

Description Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs
2000 Fairchild Semiconductor Corporation DS009885
28-Pin PLCC
100351

Truth Tables

Each Flip-flop

Synchronous Operation

Inputs

Dn L H L H X

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care t = Time before CP positive transition
= Time after CP positive transition = LOW-to-HIGH transition

Outputs Qn t+1

L H L H Qn t Qn t Qn t

Logic Diagram

Asynchronous Operation

Inputs

Outputs

Qn t+1
100351

Absolute Maximum Ratings Note 1

Storage Temperature TSTG Maximum Junction Temperature TJ VEE Pin Potential to Ground Pin Input Voltage DC Output Current DC Output HIGH ESD Note 2
−65°C to +150°C +150°C
−7.0V to +0.5V VEE to +0.5V −50 mA

Recommended Operating Conditions

Case Temperature TC Commercial
0°C to +85°C

Industrial
−40°C to +85°C

Supply Voltage VEE
−5.7V to −4.2V

Note 1 The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “Recommended Operating Conditions” table will define the conditions

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Datasheet ID: 100351QIX 512971